PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 111

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
When setting up a Synchronous Slave Reception, fol-
low these steps:
1.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear.
Address
2001 Microchip Technology Inc.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
USART Receive Register
Baud Rate Generator Register
PSPIE
PSPIF
SPEN
CSRC
Bit 7
GIE
(1)
(1)
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
CREN ADDEN
SYNC
INTE
Bit 4
TXIF
TXIE
SSPIF
SSPIE
RBIE
Bit 3
—
2.
3.
4.
5.
6.
7.
8.
9.
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
BRGH
FERR
Bit 2
T0IF
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TMR2IF TMR1IF 0000 0000 0000 0000
OERR
TRMT
Bit 1
INTF
RX9D
TX9D
Bit 0
R0IF
PIC16F87X
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
0000 000x
Value on:
POR,
BOR
DS30292C-page 109
Value on all
0000 000u
RESETS
other