PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 19

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
Address
Bank 2
Bank 3
2001 Microchip Technology Inc.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(1,3)
(3)
(1,3)
(3)
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
contents are transferred to the upper byte of the program counter.
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
INDF
OPTION_REG
PCL
STATUS
FSR
—
TRISB
—
—
—
PCLATH
INTCON
EECON1
EECON2
—
—
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
EEPGD
RBPU
Bit 7
GIE
GIE
IRP
IRP
—
—
—
—
INTEDG
PEIE
PEIE
Bit 6
RP1
RP1
—
—
—
—
—
EEPROM Data Register High Byte
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
EEPROM Address Register High Byte
Write Buffer for the upper 5 bits of the Program Counter
T0SE
INTE
INTE
Bit 4
TO
TO
—
WRERR
RBIE
Bit 3
RBIE
PSA
PD
PD
WREN
Bit 2
T0IF
T0IF
PS2
Z
Z
Bit 1
INTF
INTF
PS1
WR
DC
DC
PIC16F87X
RBIF
RBIF
Bit 0
PS0
RD
C
C
DS30292C-page 17
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
---0 0000
0000 000x
x--- x000
---- ----
0000 0000
0000 0000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
Details
41, 42
page:
on
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27
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31
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26
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41
41
41
41
27
19
26
18
27
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31
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26
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41
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