PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 206

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87X
SPI
SPI Clock Edge Select, CKE .............................................. 66
SPI Data Input Sample Phase Select, SMP ....................... 66
SPI Mode
SPI Module
SS ...................................................................................... 69
SSP .................................................................................... 65
SSP I
SSP Module
SSP Overflow Detect bit, SSPOV ...................................... 74
SSPADD Register .............................................................. 16
SSPBUF ................................................................. 17, 73, 74
SSPBUF Register .............................................................. 15
SSPCON Register .............................................................. 15
SSPCON1 .......................................................................... 73
SSPCON2 Register ............................................................ 68
SSPEN ............................................................................... 67
SSPIF ........................................................................... 22, 74
SSPM3:SSPM0 .................................................................. 67
SSPOV ................................................................... 67, 74, 84
SSPSTAT ........................................................................... 73
SSPSTAT Register ............................................................ 16
Stack .................................................................................. 26
START bit (S) ..................................................................... 66
START Condition Enable bit .............................................. 68
STATUS Register ............................................................... 18
STOP bit (P) ....................................................................... 66
STOP Condition Enable bit ................................................ 68
DS30292C-page 204
Master Mode .............................................................. 70
Master Mode Timing .................................................. 70
Serial Clock ................................................................ 69
Serial Data In ............................................................. 69
Serial Data Out ........................................................... 69
Serial Peripheral Interface (SPI) ................................ 65
Slave Mode Timing .................................................... 71
Slave Mode Timing Diagram ...................................... 71
Slave Select ............................................................... 69
SPI Clock ................................................................... 70
SPI Mode ................................................................... 69
Associated Registers ................................................. 72
Slave Mode ................................................................ 71
Block Diagram (SPI Mode) ......................................... 69
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 9
RC4/SDI/SDA Pin .................................................... 7, 9
RC5/SDO Pin ........................................................... 7, 9
SPI Mode ................................................................... 69
SSPADD .............................................................. 73, 74
SSPBUF ............................................................... 70, 73
SSPCON2 .................................................................. 68
SSPSR ................................................................. 70, 74
SSPSTAT ................................................................... 73
SSP I
SPI Master Mode ....................................................... 70
SPI Slave Mode ......................................................... 71
SSPCON1 Register .................................................... 73
Overflows ................................................................... 26
Underflow ................................................................... 26
C Bit ........................................................................... 18
DC Bit ......................................................................... 18
IRP Bit ........................................................................ 18
PD Bit ................................................................. 18, 123
RP1:RP0 Bits ............................................................. 18
TO Bit ................................................................. 18, 123
Z Bit ............................................................................ 18
2
C
2
C Operation ..................................................... 73
Synchronous Serial Port .................................................... 65
Synchronous Serial Port Enable bit, SSPEN ..................... 67
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits,
T
T1CKPS0 bit ...................................................................... 51
T1CKPS1 bit ...................................................................... 51
T1CON ............................................................................... 17
T1CON Register ................................................................ 17
T1OSCEN bit ..................................................................... 51
T1SYNC bit ........................................................................ 51
T2CKPS0 bit ...................................................................... 55
T2CKPS1 bit ...................................................................... 55
T2CON Register ...........................................................17, 55
T
Time-out Sequence ......................................................... 124
Timer0 ................................................................................ 47
Timer1 ................................................................................ 51
Timer2 ................................................................................ 55
Timing Diagrams
AD
SSPM3:SSPM0 ............................................................. 67
................................................................................... 115
Associated Registers ................................................. 49
Clock Source Edge Select (T0SE Bit) ....................... 19
Clock Source Select (T0CS Bit) ................................. 19
External Clock ............................................................ 48
Interrupt ..................................................................... 47
Overflow Enable (T0IE Bit) ........................................ 20
Overflow Flag (T0IF Bit) ......................................20, 130
Overflow Interrupt .................................................... 130
Prescaler .................................................................... 48
RA4/T0CKI Pin, External Clock ................................7, 8
T0CKI ......................................................................... 48
WDT Prescaler Block Diagram .................................. 47
Associated Registers ................................................. 54
Asynchronous Counter Mode .................................... 53
Block Diagram ........................................................... 52
Counter Operation ..................................................... 52
Operation in Timer Mode ........................................... 52
Oscillator .................................................................... 53
Prescaler .................................................................... 54
RC0/T1OSO/T1CKI Pin ............................................7, 9
RC1/T1OSI/CCP2 Pin ..............................................7, 9
Resetting of Timer1 Registers ................................... 54
Resetting Timer1 using a CCP Trigger Output .......... 53
Synchronized Counter Mode ..................................... 52
T1CON ....................................................................... 51
T1CON Register ........................................................ 51
TMR1H ...................................................................... 53
TMR1L ....................................................................... 53
Associated Registers ................................................. 56
Block Diagram ........................................................... 55
Output ........................................................................ 56
Postscaler .................................................................. 55
Prescaler .................................................................... 55
T2CON ....................................................................... 55
A/D Conversion ........................................................ 175
Acknowledge Sequence Timing ................................ 86
Baud Rate Generator with Clock Arbitration .............. 80
BRG Reset Due to SDA Collision .............................. 91
Brown-out Reset ...................................................... 164
Bus Collision
Reading and Writing to ...................................... 53
Capacitor Selection ............................................ 53
START Condition Timing ................................... 90
2001 Microchip Technology Inc.