PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 82

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87X
FIGURE 9-11:
9.2.9
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (T
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended,
leaving the SDA line held low, and the START condition
is complete.
FIGURE 9-12:
DS30292C-page 80
I
CONDITION TIMING
2
C MASTER MODE START
SDA
SCL
BRG
Value
BRG
Reload
Write to SEN bit occurs here
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
FIRST START BIT TIMING
03h
SDA
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place, and BRG starts its count
BRG
BRG
SDA = 1,
SCL = 1
T
), the
), the
BRG
01h
Set S bit (SSPSTAT<3>)
T
S
BRG
BRG decrements
(on Q2 and Q4 cycles)
00h (hold off)
DX-1
At completion of START bit,
Hardware clears SEN bit
9.2.9.1
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
1st Bit
If, at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
WCOL Status Flag
SCL allowed to transition high
T
2
03h
BRG
C module is reset into its IDLE state.
2001 Microchip Technology Inc.
02h
2nd Bit