PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 135

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 12-11:
12.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a ’0’, the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB
controller has this feature enabled, some of the
resources are not available for general use. Table 12-8
shows which features are consumed by the back-
ground debugger.
TABLE 12-8:
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
I/O pins
Stack
Program Memory
Data Memory
Note 1: XT, HS or LP oscillator mode assumed.
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
2001 Microchip Technology Inc.
2: T
3: GIE = ’1’ assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
(4)
PC
If GIE = ’0’, execution will continue in-line.
OST
Inst(PC) = SLEEP
= 1024T
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
DEBUGGER RESOURCES
PC
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
0x070 (0x0F0, 0x170, 0x1F0)
(drawing not to scale) This delay will not be there for RC osc mode.
Address 0000h must be NOP
®
Last 100h words
Inst(PC + 1)
SLEEP
0x1EB - 0x1EF
PC+1
ICD. When the micro-
RB6, RB7
1 level
PP
, V
Processor in
SLEEP
DD
, GND,
PC+2
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
12.15 Program Verification/Code
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
PC+2
Protection
Interrupt Latency
Dummy cycle
PC + 2
(2)
PIC16F87X
Inst(0004h)
Dummy cycle
0004h
DS30292C-page 133
Inst(0005h)
Inst(0004h)
0005h