PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 70

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87X
REGISTER 9-3:
DS30292C-page 68
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
bit 7
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (In I
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the
end of a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated START condition idle
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle
Legend:
R = Readable bit
- n = Value at POR
Note:
PEN: STOP Condition Enable bit (In I
RSEN: Repeated START Condition Enable bit (In I
SEN: START Condition Enable bit (In I
GCEN
R/W-0
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
2
C Master mode only)
C
2
2
C Master mode only)
C Slave mode only)
ACKEN
2
R/W-0
C Master mode only)
2
2
C Master mode only)
C Master mode only)
2
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
C Master mode only)
R/W-0
RCEN
2
C Master mode only)
R/W-0
PEN
2
C module is not in the IDLE
2001 Microchip Technology Inc.
x = Bit is unknown
R/W-0
RSEN
R/W-0
SEN
bit 0