PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 99

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1:
TABLE 10-2:
X = value in SPBRG (0 to 255)
98h
18h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Address
2001 Microchip Technology Inc.
SYNC
0
1
USART Baud Rate Generator
(BRG)
TXSTA
RCSTA
SPBRG
Name
(Asynchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Synchronous) Baud Rate = F
Baud Rate Generator Register
CSRC
SPEN
Bit 7
BRGH = 0 (Low Speed)
Bit 6
RX9
TX9
OSC
SREN
TXEN
Bit 5
, the nearest
OSC
OSC
SYNC
CREN
Bit 4
/(64(X+1))
/(4(X+1))
ADDEN
Bit 3
—
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
BRGH
FERR
Bit 2
SAMPLING
OERR
TRMT
Bit 1
OSC
Baud Rate = F
BRGH = 1 (High Speed)
/(16(X + 1)) equation can reduce the
RX9D
TX9D
Bit 0
PIC16F87X
N/A
OSC
0000 -010
0000 000x
0000 0000
Value on:
POR,
BOR
/(16(X+1))
DS30292C-page 97
0000 -010
0000 000x
0000 0000
Value on
all other
RESETS