PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 18

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87X
TABLE 2-1:
DS30292C-page 16
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
Address
Bank 1
(3)
(3)
(3)
(3)
(4)
(4)
(1,3)
(3)
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
contents are transferred to the upper byte of the program counter.
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
—
—
SSPCON2
PR2
SSPADD
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
ADRESL
ADCON1
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
PSPIE
GCEN
CSRC
ADFM
RBPU
Bit 7
SMP
IRP
GIE
IBF
—
—
—
—
(2)
ACKSTAT
INTEDG
ADIE
Bit 6
PEIE
RP1
OBF
CKE
TX9
(5)
—
—
—
—
PORTA Data Direction Register
ACKDT
TXEN
T0CS
2
IBOV
RCIE
Bit 5
T0IE
RP0
C mode) Address Register
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
ACKEN
SYNC
T0SE
Bit 4
INTE
TXIE
EEIE
TO
—
—
P
PCFG3
SSPIE
BCLIE
RCEN
RBIE
Bit 3
PSA
PD
—
—
—
S
PORTE Data Direction Bits
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PEN
PS2
R/W
—
—
Z
TMR2IE
PCFG1
RSEN
TRMT
Bit 1
INTF
POR
PS1
DC
UA
—
2001 Microchip Technology Inc.
TMR1IE
CCP2IE
PCFG0
TX9D
RBIF
Bit 0
BOR
SEN
PS0
BF
C
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
---0 0000
0000 000x
0000 0000
-r-0 0--0
---- --qq
0000 0000
1111 1111
0000 0000
0000 0000
0000 -010
0000 0000
xxxx xxxx
0--- 0000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
Details
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