PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 90

no-image

PIC16F877A-I/PT

Manufacturer Part Number
PIC16F877A-I/PT
Description
44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F877A-I/PT

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F877A-I/PT
Manufacturer:
MICROCHIP
Quantity:
9 100
Part Number:
PIC16F877A-I/PT
Manufacturer:
AVAGO
Quantity:
84
Part Number:
PIC16F877A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16F877A-I/PT
Quantity:
1 639
Part Number:
PIC16F877A-I/PT
0
Company:
Part Number:
PIC16F877A-I/PT
Quantity:
3 000
PIC16F87X
9.2.15
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-18).
FIGURE 9-18:
DS30292C-page 88
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
CLOCK ARBITRATION
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low
T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
9.2.16
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the SSP interrupt is enabled).
9.2.17
A RESET disables the SSP module and terminates the
current transfer.
SLEEP OPERATION
EFFECTS OF A RESET
T
BRG
SCL = 1, BRG starts counting
clock high interval
2001 Microchip Technology Inc.
2
C module can receive
OSC
4).

Related parts for PIC16F877A-I/PT