PIC16F877A-I/PT Microchip Technology Inc., PIC16F877A-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC16F877A-I/PT
• Description: 44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F877A-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.3
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I
pins can be configured with normal I
SMBus levels by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5:
2001 Microchip Technology Inc.
TRIS
Note 1: I/O pins have diode protection to V
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
Peripheral
OE
RD
Port
Peripheral Input
(3)
2: Port/Peripheral select signal selects between port
3: Peripheral OE (output enable) is only activated if
PORTC and the TRISC Register
data and peripheral output.
peripheral select is active.
2
C module is enabled, the PORTC<4:3>
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
(2)
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
0
1
Q
EN
D
2
DD
Schmitt
Trigger
C levels, or with
and V
V
V
N
P
SS
DD
SS
.
I/O
pin
(1)
FIGURE 3-6:
Port/Peripheral Select
Peripheral Data Out
Data Bus
WR
Port
WR
TRIS
RD
TRIS
Peripheral
OE
RD
Port
SSPl Input
Note 1: I/O pins have diode protection to V
(3)
2: Port/Peripheral select signal selects between port data
3: Peripheral OE (output enable) is only activated if
and peripheral output.
peripheral select is active.
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
(2)
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
0
1
PIC16F87X
Q
SSPSTAT<6>
CKE
EN
D
Schmitt
Trigger
DS30292C-page 33
DD
and V
Vss
1
0
V
P
N
DD
SS
Schmitt
Trigger
with
SMBus
levels
.
I/O
pin
(1)