TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 170

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

TB0RG1 is set to the sum of the TB0CPO value (c) and the one-shot pulse width (p), (c + p),
by generating the INTTB00 interrupt. TB0RG1 change must be completed before the next
match. TB0FF0 is enabled to reverse when UC matches with TB0RG1, and is disabled by
generating the INTTB01 interrupt.
If a delay is not required, TB0FF0 is reversed when data is taken into TB0CP0, and
Enable reverse when data is
taken into TB0CP0
Count clock
(Prescaler output
clock)
TB0IN input
(External trigger pulse)
Match with TB0RG1
Timer output TB0OUT pin
Fig. 9-7 One-shot Pulse Output Triggered by an External Pulse (Without Delay)
TMPM370 9-27
c
Enable reverse
Taking data into the capture register
TB0CP0. INTCAP00 generation
Pulse width
(p)
c + p
INTTB01 generation
Disable reverse when data is taken into
TB0CP1
16-bit Timer/Event Counters
Taking data into the capture
register TB0CP1
TMPM370