TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 362

no-image

TMPM370FYDFG

Manufacturer Part Number
TMPM370FYDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
QFP(14x20)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYDFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
17.6.1 Successive Conversion Using PMD A (Three Shunts) and One ADC
17.6 Usage Examples
PMD Trigger Program Registers ADAPSETn0 and ADAPSETn1. “U”, “V” and “W” indicate the
phases of a motor. AIN inputs are selected to obtain these phases.
then the interrupt signal (INTADAPDA) is generated.
Program
When a trigger input occurs, AD conversion is performed based on reg0 and reg1 sequentially, and
Example ADC settings are shown below.
Programs 0 to 5 are assigned to trigger inputs PMD0TRG0 to 5. “reg0” and “reg1” indicate the
one ADC.
reg0
reg1
INT
The following shows a circuit diagram for AD conversion using one PMD for three shunts and
W
U
V
AINA0
AINA1
AINA2
U
V
A
0
ADC A
W
V
A
1
W
U
A
TMPM370 17-46
2
PMD0TRGn
(n = 0~5)
6
V
U
A
3
PMD 0
W
4
V
A
INTADAPDA
Analog/ Digital Converter
W
U
5
A
TMPM370

Related parts for TMPM370FYDFG