TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 214

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

Receive data
write timing
Receive data
write timing
Receive data
write timing
(INTRX0 interrupt request)
(INTRX0 Interrupt request)
(INTRX0 Interrupt request)
RBFULL
RBFULL
SCLK0 output
SCLK0 output
SCLK0 output
RXD0
RXD0
RXD0
<WBUF>=“1” (if double buffering is enabled and data cannot be read from buffer 2)
Fig. 10-14 Receive Operation in the I/O Interface Mode (SCLK0 Output Mode)
<WBUF>=“1” (if double buffering is enabled and data is read from buffer 2)
Receiving data
SCLK output mode
bit
bit
In the SCLK output mode, if SC0MOD2 <WBUF> = “0” and receive double buffering is
disabled, a synchronous clock pulse is output from the SCLK0 pin and the next data is
shifted into receive buffer 1 each time the CPU reads received data. When all the 8 bits
are received, the INTRX0 interrupt is generated.
The first SCLK output can be started by setting the receive enable bit SC0MOD0
<RXE> to “1.” If the receive double buffering is enabled with SC0MOD2 <WBUF> set
to “1,” the first frame received is moved to receive buffer 2 and receive buffer 1 can
receive the next frame successively. As data is moved from receive buffer 1 to receive
buffer 2, the receive buffer full flag SC0MOD2 <RBFULL> is set to “1” and the INTRX0
interrupt is generated.
While data is in receive buffer 2, if CPU cannot read data from receive buffer 2 before
completing reception of the next 8 bits, the INTRX0 interrupt is not generated and the
SCLK0 clock stops. In this state, reading data from receive buffer 2 allows data in
receive buffer 1 to move to receive buffer 2 and thus the INTRX0 interrupt is generated
and data reception resumes.
7
7
<WBUF>=“0” (if double buffering is disabled)
bit 0
bit 0
bit 0
TMPM370 10-43
bit 1
bit 1
bit 1
bit 6
bit 6
bit 6
bit 7
bit 7
bit 7
bit 0
Serial Channel
bit 0
TMPM370