TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 488

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

Output Data
(SWDIO)
Output Data
(TDO)
Input Data
(SWDIO)
(TMS/TDI)
CLK input
(SWCLK)
(TCK)
(1) SWD Interface
(2) JTAG Interface
Low pulse width for INT0 to F
High pulse width for INT0 to F
24.7.6 Debug Communication
Ta = −40 to 85°C
24.7.5 STOP Release Interrupts
Parameter
CLK cycle
DATA hold after CLK rising
DATA valid after CLK rising
DATA valid to CLK rising
DATA hold after CLK falling
CLK cycle
DATA hold after CLK falling
DATA valid after CLK falling
DATA valid to CLK rising
DATA hold after CLK rising
Parameter
Parameter
Fig 24-2 JTAG and SWD communication timing
Symbol
T
t
dck
t
INTBH
INTBL
T
T
d2
d1
T
ds
Min.
100
100
TMPM370 24-7
Equation
T
Symbol
Symbol
dh
T
T
Tdck
Tdck
Td1
Td2
Tds
Tdh
T
T
T
T
d4
d3
d3
d4
ds
dh
Max.
Min.
Min.
100
100
20
15
20
15
4
4
-
-
Min.
100
100
80MHz
Max.
Max.
37
37
-
-
-
-
-
-
-
-
Max.
Unit
Unit
Unit
Electrical Characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMPM370