TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 85

• Manufacturer Part Number: TMPM370FYDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
• Manufacturer: Toshiba

Specifications of TMPM370FYDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 256K
• Rom Type: Flash
• Ram (kbytes): 10K
• Number Of Pins: 100
• Package: QFP(14x20)
• Vcc: 5V
• Cpu Mhz: 80
• Ssp (ch) Spi: -
• I2c/sio (ch): -
• Uart/sio (ch): 4
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 27
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Vector Engine
• Real Time Clock: -
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: 4
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit
• Lead Free Status / Rohs Status: Details

<bit0>
<bit1>
<bit2>
<bit10:8>
<bit15>
7.6.2.19
<VECTRESET>
<VECTCLRACTIVE> Clear active vector bit
<SYSRESETREQ>
<PRIGROUP>
<ENDIANESS>
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Application Interrupt and Reset Control Register
[Read] Read as 0xFA05
Endiannes
s bit
Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
[Read] Read as 0xFA05
Register key
[Write] Writing to this register requires 0x5FA in the <VECTKEY> field.
ENDIAN
ESS
R/W
15
23
31
7
0
0
0
0
1: clear all state information for active NMI, fault, and interrupts
0: do not clear.
This bit self-clears.
It is the responsibility of the application to reinitialize the stack.
System Reset Request.
1=CPU outputs a SYSRESETREQ signal. (note2)
Interrupt priority grouping
000: seven bits of pre-emption priority, one bit of subpriority
001: six bits of pre-emption priority, two bits of subpriority
010: five bits of pre-emption priority, three bits of subpriority
011: four bits of pre-emption priority, four bits of subpriority
100: three bits of pre-emption priority, five bits of subpriority
101: two bits of pre-emption priority, six bits of subpriority
110: one bit of pre-emption priority, seven bits of subpriority
111: no pre-emption priority, eight bits of subpriority
The bit configuration to split the interrupt priority register <PRI_n> into
pre-emption priority and sub priority.
Endianness bit:(Note1)
System Reset bit
1: reset system
0: do not reset system
Resets the system, with the exception of debug components (FPB, DWT
and ITM) by setting "1" and this bit is also zero cleared.
14
22
30
6
R
0
0
0
0
TMPM370 7-47
“0” is read.
29
13
21
5
R
R
0
0
0
0
“0” is read.
VECTKEY/VECTKEYSTAT
VECTKEY/VECTKEYSTAT
28
12
20
R
0
4
0
0
0
R/W
R/W
19
27
11
3
R
0
0
0
0
System
Reset
Request.
Interrupt priority grouping
RESET
REQ
SYS
R/W
R/W
10
18
26
2
0
0
0
0
PRIGROUP
Clear active
vector bit
ACTIVE
VECT
CLR
R/W
R/W
17
25
1
9
0
0
0
0
System
Reset bit
TMPM370
RESET
VECT
Interrupt
R/W
R/W
16
24
0
8
0
0
0
0