TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 396
TMPM370FYDFG
Manufacturer Part Number
TMPM370FYDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
Manufacturer
Toshiba
Datasheet
1.TMPM370FYFG.pdf
(498 pages)
Specifications of TMPM370FYDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
QFP(14x20)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYDFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Either the Single Chip or Single Boot operation mode can be selected by externally setting the level
of the
After the level is set, the CPU starts operation in the selected operation mode when the reset
condition is removed. Regarding the
operation once the mode is selected.
The mode setting method and the mode transition diagram are shown below:
(Note 1) Regarding
(Note 2) While flash auto programming or deletion is in progress, at least 0.5 microseconds
20.2.1 Reset Operation
Single chip mode
Single boot mode
To reset the device, ensure that the power supply voltage is within the operating voltage range,
that the internal oscillator has been stabilized, and that the
minimum duration of 12 system clocks (0.15 μs with 80MHz operation; the "1/1" clock gear
mode is applied after reset).
Single chip mode
BOOT
Normal mode
Characteristics”.
of reset period is required regardless of the system clock frequency.
condition, it takes approx. 2 ms to enable reading after reset.
User to set the
switch method
(PF0) pin while the device is in reset status.
Operation mode
Fig. 20-2 Mode Transition Diagram
Table 20-2 Operation Mode Setting
to power-on, refer to section “Power On Reset” and “Electric
boot mode
User
TMPM370 20-4
BOOT
Onboard
programming mode
(PF0) pin, be sure not to change the levels during
boot mode
Single
RESET
0 → 1
0 → 1
Pin
RESET
Reset state
Flash Memory Operation
BOOT (PF0)
input is held at "0" for a
1
0
TMPM370
In this
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