TMPM370FYDFG Toshiba, TMPM370FYDFG Datasheet - Page 187

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TMPM370FYDFG

Manufacturer Part Number
TMPM370FYDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 256K FLASH, 10K RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMPM370FYDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
10K
Number Of Pins
100
Package
QFP(14x20)
Vcc
5V
Cpu Mhz
80
Ssp (ch) Spi
-
I2c/sio (ch)
-
Uart/sio (ch)
4
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
27
16-bit Timer / Counter
8
Motor / Igbt Control
Vector Engine
Real Time Clock
-
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
4
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM370FYDFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
10.3.9
10.3.10 Transmit Control Unit
I/O interface mode:
Asynchronous (UART) mode:
TXDCLK
The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of
the receive counter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th
clock pulse.
SIOCLK
Transmit Counter
When the CPU writes data to the transmit buffer, data transmission is initiated on the
rising edge of the next TXDCLK and the transmit shift clock (TXDSFT) is also generated.
In the SCLK output mode with SC0CR <IOC> set to “0,” each bit of data in the transmit
buffer is output to the TXD0 pin on the rising edge of the shift clock output from the
SCLK0 pin.
In the SCLK input mode with SC0CR <IOC> set to “1,” each bit of data in the transmit
buffer is output to the TXD0 pin on the rising or falling edge of the input SCLK signal
according to the SC0CR <SCLKS> setting.
15
16
1
Fig. 10-5 Transmit Clock Generation
2
3
TMPM370 10-16
4
5
6
7
8
9
10
11
12
13
14
15
Serial Channel
16
TMPM370
1
2

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