TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 110

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8 Exceptions
IMCGC
8.6.3.3
(Note 1)
(Note 2)
CG Interrupt Mode Control Register C
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
“0” is read. Active state setting of INTRTC
“0” is read. Active state setting of INT6 standby
“0” is read. Active state setting of INT7 standby
“0” is read. Active state setting of INTRMCRX1
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the
<INTxEN>. Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
Set it as shown below.
clear request. (101~111: setting
prohibited)
clear request. (101~111: setting
prohibited)
standby clear request.
Set it as shown below.
standby clear request.
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
010: Falling edge
100: Both edges
0
100: Both edges
011: Rising edge
EMCGA2
EMCGB2
EMCG82
EMCG92
14
22
30
6
0
0
0
Under development
EMCGA1
EMCGB1
EMCG81
EMCG91
R/W
R/W
R/W
R/W
13
21
29
Page98
5
1
1
1
1
EMCG80
EMCG90
EMCGA0
EMCGB0
12
20
28
4
0
0
0
0
Active state of INT6
standby clear request.
Active state of INT7
standby clear request.
Active state of
INTRMCRX1 standby
clear request.
Active state of INTRTC
standby clear request.
00: －
01: Rising edge
10: Falling edge
00: －
01: Rising edge
10: Falling edge
00: －
01: Rising edge
10: Falling edge
00: －
01: Rising edge
10: Falling edge
11: Both edges
11: Both edges
11: Both edges
11: Both edges
EMSTA1
EMSTB1
EMST81
EMST91
11
19
27
3
0
0
0
0
R
R
R
R
EMSTA0
EMSTB0
EMST80
EMST90
10
18
26
2
0
0
0
0
“0” is read. INTRTC
“0” is read. INT6 clear
“0” is read. INT7clear
“0” is read. INTRMC
17
25
1
R
9
R
R
R
0
0
0
0
clear input
0: Disable
1: Enable
input
0: Disable
1: Enable
input
0: Disable
1: Enable
RX1 clear
input
0: Disable
1: Enable
INTAEN
INT8EN
INTBEN
INT9EN
TMPM330
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0