TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 217
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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The channel 0 registers are described here. Each register for all the channels operates in the same way.
11.4 Register Description (Only for Channel 0)
11.4.1
11.4.2
SC0BUF
SC0EN
<SIOE>:
<TB7:0>
<RB7:0>
SC0BUF works as a transmit buffer for WR operation and as a receive buffer for
RD operation.
Enable register
Buffer register
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
To use the SIO, enable the SIO operation.
When the operation is disabled, no clock is supplied to the other registers in the SIO module.
This can reduce the power consumption.
If the SIO operation is executed and then disabled, the settings will be maintained in each
register.
Transmit buffer (at WR operation).
Specified the SIO operation.
Receive buffer (at RD operation).
Function
Function
“ 0 ” is read.
TB7/RB7
7
7
0
TB6/RB6
Under development
6
6
0
Page205
TB5/RB5
5
5
0
TB7~0 : Transmit buffer/FIFO
RB7~0 : Receive buffer/FIFO
TB4/RB4
R
4
4
0
0
R/W
TB3/RB3
3
3
0
TB2/RB2
2
2
0
TB1/RB1
1
1
0
TMPM330
SIO
operation
0:
disabled
1:
enabled
TB0/RB0
SIOE
R/W
0
0
0
0
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