TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 337

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

14.3.1.6 Reception Completion
interrupt is generated, the RMCRSTAT <RMCDMAXIF> bit is set to “1”.
generated, the RMCRSTAT <RMCLOIF> bit is set to “1”.
1) Completed by a maximum data bit cycle
Detecting a maximum data bit cycle completes reception and generates an interrupt. After the
2) Completed by excess low width
Detecting excess low width completes reception and generates an interrupt. After the interrupt is
Threshold: < RMCLL7:0>
Excess low width is detected when signal stay
low longer than specified.
Under development
Threshold: <RMCDMAX7:0>
If the falling edge of the data bit cycle isn’t monitored after time
specified as threshold, a maximum data bit cycle is detected.
The detection completes reception and generates an interrupt.
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Excess low width detection
interrupt
Maximum
interrupt
data
TMPM330
bit
cycle