TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 205

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

The CPU will read the data from either the second receive buffer (SC0BUF) or from the
receive FIFO (the address is the same as that of the receive buffer). If the receive FIFO has
not been enabled, the receive buffer full flag <RBFLL> is cleared to “0” by the read
operation. The next data received can be stored in the first receive buffer even if the CPU
has not read the previous data from the second receive buffer (SC0BUF) or the receive
FIFO.
If SCLK is set to generate clock output in the I/O interface mode, the double buffer control
bit SC0MOD2 <WBUF> can be programmed to enable or disable the operation of the
second receive buffer (SCOBUF).
By disabling the second receive buffer (i.e., the double buffer function) and also disabling
the receive FIFO (SCOFCNF <CNFG> = 0 and <FDPX1:0> = 01), handshaking with the
other side of communication can be enabled and the SCLK output stops each time one
frame of data is transferred. In this setting, the CPU reads data from the first receive buffer.
By the read operation of CPU, the SCLK output resumes.
If the second receive buffer (i.e., double buffering) is enabled but the receive FIFO is not
enabled, the SCLK output is stopped when the first receive data is moved from the first
receive buffer to the second receive buffer and the next data is stored in the first buffer filling
both buffers with valid data. When the second receive buffer is read, the data of the first
receive buffer is moved to the second receive buffer and the SCLK output is resumed upon
generation of the receive interrupt INTRX. Therefore, no buffer overrun error will be caused
in the I/O interface SCLK output mode regardless of the setting of the double buffer control
bit SC0MOD2 <WBUF>.
If the second receive buffer (double buffering) is enabled and the receive FIFO is also
enabled (SCNFCNF <CNFG> = 1 and <FDPX1:0> = 01/11), the SCLK output will be
stopped when the receive FIFO is full (according to the setting of SCOFNCF <RFST>) and
both the first and second receive buffers contain valid data. Also in this case, if SCOFCNF
<RXTXCNT> has been set to “1,” the receive control bit RXE will be automatically cleared
upon suspension of the SCLK output. If it is set to “0,” automatic clearing will not be
performed.
In other operating modes, the operation of the second receive buffer is always valid, thus
improving the performance of continuous data transfer. If the receive FIFO is not enabled,
an overrun error occurs when the data in the second receive buffer (SC0BUF) has not been
read before the first receive buffer is full with the next receive data. If an overrun error
occurs, data in the first receive buffer will be lost while data in the second receive buffer and
the contents of SC0CR <RB8> remain intact. If the receive FIFO is enabled, the FIFO must
be read before the FIFO is full and the second receive buffer is written by the next data
through the first buffer. Otherwise, an overrun error will be generated and the receive FIFO
overrun error flag will be set. Even in this case, the data already in the receive FIFO remains
intact.
The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the
9-bit UART mode will be stored in SC0CR <RB8>.
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by
(Note) In this mode, the SC0CR <OEER> flag is insignificant and the operation is
undefined. Therefore, before switching from the SCLK output mode to
another mode, the SC0CR register must be read to initialize this flag.
Under development
Page193
TMPM330