TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 354

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15 Analog/Digital Converter
ADREG2AH
ADREG2AL
ADREG3BL
ADREG3BH
•
•
•
conve rted value is stored. A read of a lower register (ADREGxL) will set this bit to "0”.
both conversion result storage registers (ADREGxH,ADREGxL) are read. A read of a flag will clear this bit to "0.
registers.
Bit 0 of the ADREG2AL/ADREG3BL is the A/D conversion result storage flag <ADRxRF>. It is set to "1" after an A/D
Bit 1 of the ADREG2AL/ADREG3BL is the over RUN flag <OVRx>. It is set to "1" if a conversion result is overwritten before
When reading conversion result storage registers on a byte-by-byte basis, first read upper registers and then read lower
Converted channel x value
bit Symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Function
Function
A/D conversion result
A/D conversion result
ADR21
Store lower 2 bits of
ADR29
ADR31
Store lower 2 bits of
ADR39
7
7
7
7
Fig. 15-9 A/D Conversion Result Register
Lower A/D Conversion Result Register 2A
Upper A/D Conversion Result Register 2A
Lower A/D Conversion Result Register 3B
Upper A/D Conversion Result Register 3B
R
R
A DREGxH
0
0
9
ADR20
ADR28
ADR30
ADR38
7
6
6
6
6
8
6
7
Under development
5
"0" is read.
"0" is read.
ADR27
ADR37
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Store upper 8 bits of A/D conve rsion result
Store upper 8 bits of A/D conve rsion result
4
6
5
5
5
5
3
5
2
4
ADR26
ADR36
1
4
4
4
4
3
0
R
0
R
0
R
0
R
0
2
ADR25
ADR35
3
3
3
3
1
7
6
0
5
ADR24
ADR34
2
2
2
2
4
3
Over RUN
flag
0:Not
generate
1: Generate
Over RUN
flag
0:Not
generate
1: Generate
ADR23
ADR33
2
OVR2
OVR3
1
R
1
1
R
1
0
0
ADREGxL
1
0
TMPM330
A/D
conversion
result storage
flag
1: Presence of
conversion
result
A/D
conversion
result storage
flag
1: Presence of
conversion
result
ADR2RF
ADR3RF
ADR22
ADR32
R
R
0
0
0
0
0
0