TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 479

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SCL clock frequency
Hold time for START condition
SCL low width (Input) (Note 1)
SCL high width (Input) (Note 2)
Setup time for a repeated START
condition
Data hold time (Input) (Note 3, 4)
Data setup time
Setup time for a stop condition
Bus free time between stop condition
and start condition
AC measurement condition
(Note 1) SCL clock low width (output) is calculated with: (2
(Note 2) SCL clock high width (output) is calculated with: (2
(Note 3) The output data hold time is equal to 12x of internal SCL.
(Note 4) The Philips I2C-bus specification states that a device must internally provide a hold time of
(Note 5) Software-dependent.
(Note 6) The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is
(1) I2C Mode
21.5.2
Notice: On I2C-bus specification, Maximum Speed of Standard Mode is 100KHz, Fast mode is
400Khz. Internal SCL Frequency setting should comply with Note1 & Note2 shown above.
/Input levels: Refer to low-level input voltage and high-level input voltage in 21.2 DC Electrical
/Output levels: High 0.8DVCC3 V/Low 0.2DVCC3V, CL=30 pF
fsys cycle time. It varies depending on the programming of the clock gear function.
SBInCR.
at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
However, this SBI does not satisfy this requirement. Also, the output buffer for SCL does not
incorporate slope control of the falling edges; therefore, the equipment manufacturer should
design so that the input data hold time shown in the table is satisfied, including tr/tf of the
SCL and SDA lines.
switched off, the SDA and SCL I/O pins must be floating so that they don’t obstruct the bus
lines. However, this SBI does not satisfy this requirement.
Parameter
In the table below, the letter x represents the I2C operation clock cycle time which is identical to the
n denotes the value of n programmed into the SCK (SCL output frequency select) field in the
SBI（I2C）
Characteristics.
Symbol
t
t
t
t
t
t
t
t
t
SCL
HD:STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
(Note 5)
(Note 5)
Min
Under development
0
-
-
-
-
-
-
Equation
Page467
Max
-
-
-
-
-
-
-
-
-
Standard Mode
Min
250
4.0
4.7
4.0
4.7
0.0
4.0
4.7
0
n-1
n-1
+58)/x
+12)/x
Max
100
-
-
-
-
-
-
-
-
Min
100
0.6
1.3
0.6
0.6
0.0
0.6
1.3
Fast Mode
0
Max
400
-
-
-
-
-
-
-
-
TMPM330
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs