TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 290

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.2.7
Receive Control Register 1 [CECRCR1]
bit Symbol
Read/Write
After reset
Read/Write
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
Function
Function
Function
“0” is read.
“0” is
read.
“0” is
read.
31
23
15
―
―
R
7
R
0
0
―
R
0
CECMIN2
Time to identify as min. cycle error
000: 2.05ms
001: 2.05ms+1cycle
010: 2.05ms+2cycles
011: 2.05ms+3cycles
100: 2.05ms-1cycle
101: 2.05ms-2cycles
110: 2.05ms-3cycles
111: 2.05ms-4cycles
Point of determining the data as 0
or 1.
000: 1.05ms
001: 1.05ms+2cycles
010: 1.05ms+4cycles
011: 1.05ms+6cycles
100: 1.05ms-2cycles
101: 1.05ms-4cycles
110: 1.05ms-6cycles
111: Reserved
CECDAT
30
22
14
6
2
Under development
The number of “1”
samplings for noise
cancellation.
00: 1
01: 2
10: 3
11: 4
CECMIN1
CECHNC
Page278
CECDAT
R/W
R/W
29
21
13
5
1
0
1
0
R/W
0
“0” is read.
CECMIN0
CECHNC
CECDAT
28
20
12
―
R
4
0
0
0
Cycle to identify
timeout
“0” is
read.
“0” is
read.
00: 1 bit cycle
01: 2 bit cycles
10: 3 bit cycles
11: Reserved
CECTOU
27
19
11
T1
―
―
R
R
3
0
0
R/W
0
The number of “0” samplings for
noise cancellation.
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
Time to identify as max. cycle error
000: 2.75ms
001: 2.75ms+1cycle
010: 2.75ms+2cycles
011: 2.75ms+3cycles
100: 2.75ms-1cycle
101: 2.75ms-2cycles
110: 2.75ms-3cycles
111: 2.75ms-4cycles
CECMAX
CECTOU
CECLNC
26
18
10
T0
2
2
2
Error
interrupt
suspend
0: Yes
1: No
CECMAX
CECLNC
CECRI
R/W
R/W
HLD
R/W
25
17
9
1
1
0
1
0
0
TMPM330
Logical
“0” as
ACK
response
0: send
1: not
send
Data
reception
at logical
address
discrepan
cy
0: Yes
1: No
CECMAX
CECOTH
CECACK
CECLNC
R/W
R/W
DIS
24
16
8
0
0
0
0
0