TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 353

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

ADREG08L
ADREG19H
ADREG08H
ADREG19L
•
•
•
Converted channel x value
Bit 0 of ADREG08L/ADREG19L is the A/D conversion result storage flag <ADRxRF>. This bit is set to "1" after an
A/D converted value is stored. A read of a lower register (ADREGxL) will set this bit to "0".
Bit 1 of ADREG08L/ADREG19L is the over RUN flag <OVRx>. This bit is set to "1" if a conversion result is
overwritten before both conversion result storage registers (ADREGxH and ADREGxL) are read. A read of a flag will
clear this bit to "0."
When reading conversion result storage registers on a byte-by-byte basis, first read upper registers and then read
lower registers.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Function
Function
Function
Store lower 2 bits of
A/D conversion result
Store lower 2 bits of
A/D conversion result
ADR01
ADR09
ADR11
ADR19
7
7
7
7
Fig. 15-8 A/D Conversion Result Register
Lower A/D Conversion Result Register 08
Upper A/D Conversion Result Register 08
Lower A/D Conversion Result Register 19
Upper A/D Conversion Result Register 19
R
R
0
0
ADREGxH
9
ADR00
ADR08
ADR10
ADR18
7
6
6
6
6
8
6
Under development
7
5
“0” can be read.
“0” can be read.
Page341
ADR07
ADR17
Store upper 8 bits of A/D conversion result
Store upper 8 bits of A/D conversion result
4
6
5
5
5
5
3
5
2
4
ADR06
ADR16
1
4
4
4
4
3
0
R
R
R
R
0
0
0
0
2
ADR05
ADR15
1
3
3
3
3
7
6
0
5
ADR04
ADR14
2
2
2
2
4
3
Over RUN
flag
0:
Not
generate
1: Generate
Over R UNflag
0: N ot
generate
1: Generate
ADR03
ADR13
2
OVR0
OVR1
1
R
0
1
1
R
0
1
ADREGxL
1
TMPM330
0
A/D
conversion
result
storage flag
1:Presence
of
conversion
result
A/D
conversion
result storage
flag
1:Presence of
conversion
result
ADR0RF
ADR1RF
ADR02
ADR12
0
R
0
0
R
0
0
0