TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 352

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15 Analog/Digital Converter
(Note 1) If AD conversion is executed with the match triggers <ADHTG> and <HADHTG> of a
(Note 2)Do not make a top-priority AD conversion setting and a normal AD conversion setting
(Note 3) The external trigger cannot be used for H/W activation of AD conversion when it is
(Note 4) A software reset initializes other bits. Resetting a mode register is needed.
(Note) The TMPM330 disables the external trigger used for H/W activation. Therefore “0”
ADMOD4
16-bit timer set to "1" by using a source for triggering H/W, A/D conversion can be
activated at specified intervals by performing three steps shown below when the timer
is idle:
1.
2.
3.
simultaneously.
used for H/W activation of top priority AD conversion.
cannot be set to <HADHS> and <ADHS>.
Select a source for triggering HW: <ADHS>, <HADHS>
Enable H/W activation of AD conversion: <ADHTG>, <HADHTG>
Start the timer.
Bit symbol
Read/Write
After reset
Function
HW source for
activating
top-priority
A/D
conversion
0: External
1:Match with
Fig. 15-7 A/D Mode Control Register 4
HADHS
TRG
TB5RG0
7
0
HW for
activating
top-priority
A/D
conversion
0: Disable
1: Enable
HADHTG
Under development
6
0
A/D Mode Control Register 4
Page340
R/W
HW source for
activating
normal A/D
conversion
0: External
1:Match with
TB6RG0
TRG
ADHS
5
0
HW for
activating
normal A/D
conversion
0: Disable
1: Enable
ADHTG
4
0
“0” can be read.
3
R
0
2
Overwriting 10 with 01 allows
ADC to be software reset.
ADRST1
TMPM330
－
W
1
ADRST0
Ｗ
－
0