TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 445

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Read
Read/Reset
ID-Read
Automatic page
programming
Automatic chip
erase
Auto
Block erase
Protection bit
programming
Protection bit
erase
Command
sequence
(Note 1) Always set "0" to the address bits [1:0] in the entire bus cycle. (Recommendable setting
(Note 2) Bus cycles are "bus write cycles" except for the second bus cycle of the Read command,
(6) List of Command Sequences
values to bits [7:2] are ”0”.)
the fourth bus cycle of the Read/reset command, and the fifth bus cycle of the ID-Read
command. Bus write cycles are executed by 32-bit data transfer commands. The address
[31:16] in each bus write cycle should be the target flash memory address [31:16] of the
command sequence. Use "Addr." in the table for the address [15:0].
Supplementary explanation
• RA:
• RD:
• IA:
• ID:
• PA:
• BA:
• PBA: Protection bit address
First bus
PD:
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
Addr.
cycle
Data
0xXX
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
0xAA
0xF0
Read address
Read data
ID address
ID data
Program page address
Program data (32 bit data)
After the fourth bus cycle, enter data in the order of the address for a page.
Block address
Table 18-17 Flash Memory Access from the Internal CPU
Second bus
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
0xAAXX
Addr.
cycle
Data
0x55
0x55
0x55
0x55
0x55
0x55
0x55
－
－
Third bus
Under development
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
0x54XX
cycle
Addr.
Data
0xA0
0x9A
0x6A
0xF0
0x90
0x80
0x80
－
－
Page433
Fourth bus
0x54XX
0x54XX
0x54XX
0x54XX
Addr.
cycle
Data
0xAA
0xAA
0xAA
0xAA
0x00
PD0
RD
RA
PA
－
－
IA
Fifth bus
0xAAXX
0xAAXX
0xAAXX
0xAAXX
Addr.
cycle
Data
0xXX
0x55
0x55
0x55
0x55
PD1
PA
－
－
－
－
ID
Sixth bus
0x54XX
0x54XX
0x54XX
Addr.
cycle
Data
0x9A
0x6A
0x10
0x30
PD2
PA
BA
－
－
－
－
－
－
Seventh bus
TMPM330
cycle
Addr.
Data
0x9A
0x6A
PD3
PBA
PBA
PA
－
－
－
－
－
－
－
－
－
－