TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 180

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10 16-bit Timer/Event Counters (TMRBs)
10.5.2
10.5.3
UC0 is a 16-bit binary counter.
two registers are built into each channel. If the comparator detects a match between a value set
in this timer register and that in a UC0 up-counter, it outputs the match detection signal.
Up-counter (UC0)
Timer registers (TB0RG0, TB0RG1)
TB0RG0 and TB0RG1 are registers for setting values to compare with up-counter values and
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types - φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TB0IN0
pin.
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<TB0RUN> = “1”, and stops counting and clears counter value if <TB0RUN> = “0”.
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•
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double-buffered configuration. The two registers use TB0CR<TB0WBF> to control the
enabling/disabling of double buffering. If <TB0WBF> = “0”, double buffering is disabled and
if <TB0WBF> = “1”, it is enabled. If double buffering is enabled, data is transferred from
register buffer 0 to the TB0RG0 and TB0RG1 timer registers when there is a match
between UC0 and TB0RG1.
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the double buffer.
UC0 source clock, specified by
Counter operation is specified by TB0RUN<TB0RUN>. UC0 starts counting if
1) When a match is detected
2) When UC0 stops
UC0 stops counting and clears counter value if TB0RUN <TB0RUN> = “0”.
If UC0 overflow occurs, the INTTB0 overflow interrupt is generated.
TB0RG0 and TB0RG1 of this timer registers are paired with register buffer 0 - a
The values of TB0RG0 and TB0RG1 become undefined after a reset. A reset disables
By setting TB0MOD<TB0CLE> = “1”, UC0 is cleared if when the comparator detects a
match between counter value and the value set in TB0RG1. UC0 operates as a
free-running counter if TB0MOD<TB0CLE> = “0”.
Source clock
Count start/ stop
Timing to clear UC0
UC0 overflow
Configuration
Default setting
Under development
Page168
TB0MOD<TB0CLK1:0>
, can be selected from either three
TMPM330