TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 212
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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11 Serial Channel (SIO)
Transmit buffer 1
Transmit Buffer 2
TX FIFO
TBEMP
INTTX0
TXE
I/O interface mode with SCLK input (normal mode):
The following example describes the case a 4-byte data stream is transmitted:
SC0TFC <7:6> = 000000: Sets the interrupt to be generated at fill level 0.
SC0FCNF <4:0> = 01001: Allows continued transmission after reaching the fill level.
In this condition, data transmission can be initiated along with the input clock by setting the
transfer mode to half duplex, writing 4 bytes of data to the transmit FIFO, and setting the
<TXE> bit to “1.” When the last transmit data is moved to the transmit buffer, the transmit
FIFO interrupt is generated.
SC0TFC <1:0> = 01: Clears the transmit FIFO and sets the condition of interrupt
generation.
Data 1
Data 6
Data 5
Data 4
Data 3
Data 2
Fig. 11-9 Transmit FIFO Operation
Under development
Page200
Data 3
Data 6
Data 5
Data 4
Data 2
Data 4
Data 6
Data 5
Data 3
Data 5
Data 6
Data 4
Data 6
Data 5
TMPM330
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