TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 168

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

TBnFFCR
(0x4001_0xx0)
10 16-bit Timer/Event Counters (TMRBs)
＜TBnFF0C1:0＞:Controls the timer flip-flop.
＜TBnE1:0＞:Reverses the timer flip-flop when the up-counter matches the timer register 0,1 (TBnRG0,1).
＜TBnC1:0＞:Reverses the timer flip-flop when the up-counter value is taken into the capture register 0,1
10.4.1.5 TMRB flip-flop control register (channels 0 through 9)
“00”: Reverses the value of TBnFF0 (reverse by using software).
“01”: Sets TBnFF0 to “1”.
“11”:Don’t care
“10”: Clears TBnFF0 to “0”.
(TBnCP0,1).
Read/Write
Read/Write
Read/Write
bit Symbol
Read/Write
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
“11” is read.
31
23
15
R
R
R
7
0
0
0
1
R
TMRBn flip-flop control register (n=0~9)
30
22
14
R
R
R
6
1
0
0
0
When the
up-counter
value is
taken into
TBnCP1
TBnC1T1
TBnFF0 reverse trigger
0: Disable trigger
1: Enable trigger
Under development
29
21
13
R
R
R
5
0
0
0
0
Page156
When the
up-counter
value is
taken into
TBnCP0
TBnC0T1
28
20
12
R
R
R
4
0
0
0
0
R/W
When the
up-counter
matches
TBnRG1
TBnE1T1
27
19
11
R
R
R
3
0
0
0
0
When the
up-counter
matches
TBnRG0
TBnE0T1
26
18
10
R
R
R
2
0
0
0
0
TBnFF0 control
00: Invert
01: Set
10: Clear
11: Don't care
* This is always read as
“11.”
TBnFF0C1 TBnFF0C0
25
17
R
R
9
R
1
0
0
0
1
R/W
24
16
R
R
8
R
0
0
0
0
1
TMPM330