TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 42
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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Price
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6 Reset
6.2
6.2.1 Reset Period
6.2.2 After Reset
(Note 1)
Warm Reset
internal high-frequency oscillator is providing stable oscillation. To reset the TMPM330, assert the
internal I/O registers. Registers that are only initialized by a cold reset are registers related to the
processor core’s system debug components (FPB, DWT, ITM), the clock generator’s reset flag and
the Flash security bit.
needed.
service routine.
RESET
As a precondition, ensure that the power supply voltage is within the operating range and the
A warm reset initializes the majority of the Cortex-M3 processor core’s system control registers and
After reset, the PLL multiplication circuit is inactive and must be enabled in the PLLSEL register if
When the reset exception handling is completed, the program branches to the reset interrupt
signal (active low) for a minimum duration of 12 system clocks.
The reset operation may alter the internal RAM state.
Under development
Page30
TMPM330
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