PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 137

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

5.4
5.4.1
Activated with bit FMR1.PMOD = 1.
PCM line bit rate
Single frame length
Framing frequency
Organization
Selection of one of the four permissible framing formats is performed by bits
FMR4.FM1...0. These formats are:
F4
F12
ESF
F72
The operating mode of the FALC
and characteristics, line code, multiframe structure, and signaling scheme.
The FALC
24 (T1, 1.544 Mbit/s) carriers. The internal HDLC-Controller supports all signaling
procedures including signaling frame synchronization/synthesis in all framing formats.
After RESET, the FALC
T1(PCM24) mode. Switching between the framing formats is done via bit FMR4.FM1/0
for the receiver and for the transmitter.
5.4.2
Synchronization status is reported via bit FRS0.LFA (Loss Of Frame Alignment).
Framing errors (pulse frame and multiframe) are counted by the Framing Error Counter
FEC.
Loss of Frame Alignment (FRS0.LFA or opt. FRS0.LMFA) is declared if:
2 out of 4 framing bits or
2 out of 5 framing bits or
2 out of 6 framing bits in F4/12/72 format or
2 out of 6 framing bits per multiframe period in ESF format or
4 consecutive multiframe pattern in ESF format are incorrect.
It depends on the selected multiframe format and optionally on bit FMR2.SSP which
framing bits are observed:
F4:FT bits
F12, F72:SSP = 0: FT bits
Data Sheet
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®
Framer Operating Modes (T1/J1)
General
General Aspects of Synchronization
-LH implements all of the standard and/or common framing structures PCM
4-frame multiframe
12-frame multiframe (D4)
Extended Superframe (F24)
72-frame multiframe (SLC96)
FRS0.LFA
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®
-LH must be programmed with FMR1.PMOD = 1 to enable the
1.544 Mbit/s
193 bit, No. 1 … 193
8 kHz
24 time slots, No. 1 … 24
with 8 bits each, No. 1 … 8 and one preceding F bit
FRS0.LFA: FS bits
®
-LH is selected by programming the carrier data rate
137
FRS0.LFA
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07