PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 196

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

PMOD…
XFS…
ECM…
IMOD…
XAIS…
Data Sheet
PCM Mode
For E1 application this bit must be set low. Switching from E1 to T1 or
vice versa the device needs up to 10 s to settle up to the internal
clocking.
0…
1…
Transmit Framing Select
Selection of the transmit framing format could be done independent
of the receive framing format.
0…
1…
Error Counter Mode
The function of the error counters is determined by this bit.
0
1…
Select System Interface Mode
0... 4.096 Mbit/s
1... 2.048 Mbit/s
Transmit AIS Towards Remote End
Sends AIS via ports XL1, XL2, XOID towards the remote end. The
outgoing data stream which could be looped back via the Local Loop
to the system interface is not affected.
PCM 30 or E1 mode.
PCM 24 or T1 mode.
Doubleframe format enabled.
CRC4-multiframe format enabled.
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters are reset with the rising
edge of the corresponding bits in the DEC register.
Every second the error counters are latched and then
automatically be reset. The latched error counter state should
be read within the next second. Reading the error counter
during updating should be avoided (do not access an error
counter within 2 µs before or after the one-second interrupt
occurs).
196
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07