PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 293

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Line Interface Mode 1 (Read/Write)
Value after RESET: 00
EFSC…
RIL2…RIL0…
Note: LIM1.RIL(2:0) must be programmed before LIM0.EQON = 1 is set.
DCOC
Data Sheet
LIM1
EFSC
7
Enable Frame Synchronization Pulse
0…
1…
Receive Input Threshold
Only valid if analog line interface and short haul mode is selected
(LIM1.DRS=0 and LIM1.EQON = 0).
No signal is declared if the voltage between pins RL1 and RL2 drops
below the limits programmed via bits RIL2...0 and the received data
stream has no transition for a period defined in the PCD register.
The threshold where no signal is declared is programmable via the
RIL2...0 bits. See
details.
DCO-R and DCO-X Control
0…
1…
RIL2
H
The transmit clock is output on pin XCLK
Pin XCLK provides an 8 kHz frame synchronization pulse which
is active for one 2.048-MHz cycle (488 ns)
1.544-MHz reference clock for the DCO-R/DCO-X circuitry
provided on pin SYNC/SYNC2.
2.048-MHz reference clock for the DCO-R/DCO-X circuitry
provided on pin SYNC/SYNC2.
RIL1
RIL0
Table 58 "DC Parameters" on page 336
293
DCOC
JATT
RL
FALC-LH V1.3
T1/J1 Registers
DRS
0
PEB 2255
2000-07
(35)
for