PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 312

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Framer Receive Status Register 1 (Read)
EXZD…
PDEN…
LLBDD…
LLBAD…
Data Sheet
FRS1
EXZD
7
Excessive Zeros Detected
Significant
(FMR2.EXZE=1).
Set after detecting of more than 7 (B8ZS code) or more than 15 (AMI
code) contiguous zeros in the received bit stream. This bit is cleared
when read.
Pulse Density Violation Detected
The pulse density of the received data stream is below the
requirement defined by ANSI T1. 403 or more than 15 consecutive
zeros are detected. With the violation of the pulse density this bit is
set and remains active until the pulse density requirement is fulfilled
for 23 consecutive ’1’ pulses.
Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
Line Loop Back Deactivation Signal Detected
This bit is set in case the LLB deactivate signal is detected and then
received over a period of more than 33,16 ms with a bit error rate less
than 1/100. The bit remains set as long as the bit error rate does not
exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes a LLBSC interrupt.
Line Loopback Activation Signal Detected/PRBS Status
Depending on bit LCR1.EPRM the source of this status bit changed.
LCR1.EPRM=0: This bit is set in case the LLB activate signal is
detected and then received over a period of more than 33,16 ms with
a bit error rate less than 1/100. The bit remains set as long as the bit
error rate does not exceed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation.
Any change of this bit causes a LLBSC interrupt.
PDEN
only
LLBDD
if
312
excessive
LLBAD
zeros
detection
XLS
FALC-LH V1.3
T1/J1 Registers
XLO
0
is
PEB 2255
enabled
2000-07
(4D)