PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 119

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

PCI Configuration Registers
Register 10-3. (PCISR; PCI:06h) PCI Status
Register 10-4. (PCIREV; PCI:08h) PCI Revision ID
Register 10-5. (PCICCR; PCI:09-0Bh) PCI Class Code
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
23:16
10:9
15:8
Bit
Bit
Bit
3:0
6:5
7:0
7:0
11
12
13
14
15
4
7
8
Reserved.
New Capability Functions Support. Writing 1 supports New Capabilities
Functions. If enabled, the first New Capability Function ID is located at the
PCI Configuration Space offset determined by the New Capabilities linked list
pointer value at offset 34h. Can be written only from the serial EEPROM.
Read-only from the PCI Bus.
Reserved.
Fast Back-to-Back Capable. Writing 1 indicates an adapter can accept fast
back-to-back transactions.
Note:
Master Data Parity Error. Not Supported.
DEVSEL# Timing. Indicates timing for DEVSEL# assertion. Writing 01 sets
this bit to medium.
Note:
Signaled Target Abort. When set to 1, indicates the PCI 9030 signaled
a Target Abort. Writing 1 clears this bit to 0.
Received Target Abort. When set to 1, indicates the PCI 9030 received
a Target Abort signal. Not Supported.
Received Master Abort. When set to 1, indicates the PCI 9030 received
a Master Abort signal. Not Supported.
Signaled System Error. When set to 1, indicates the PCI 9030 reported
a system error on SERR#. Writing 1 clears this bit to 0.
Detected Parity Error. When set to 1, indicates the PCI 9030 detected a
PCI Bus parity error, even if parity error handling is disabled [the Parity Error
Response bit in the Command register is clear (PCICR[6]=0].
This bit is set when the PCI 9030 detects a parity error during a PCI Address
phase or a PCI Data phase when it is the Target of a write.
Writing 1 clears this bit to 0.
Revision ID. PCI 9030 Silicon revision.
Register Level Programming Interface. None defined.
Subclass Code (Other Bridge Device).
Base Class Code (Bridge Device).
Hardwired to 1.
Hardwired to 01.
Description
Description
Description
Read
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Yes/Clr
Yes/Clr
Yes/Clr
Write
Write
Serial
Write
Serial
Serial
Serial
Serial
No
No
No
No
No
No
No
Current Rev #
Value after
Value after
Value after
Section 10
Reset
Reset
Reset
Registers
80h
06h
0h
01
0h
1
0
1
0
0
0
0
0
0
10-5