PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 154

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
Table 11-2. Input Pin Pull-Up and Pull-Down
Resistor Requirements (Continued)
Note:
on TDI, TMS, and TRST#. To remain compliant with PCI r2.2, no
internal pull-up resistors are provided on JTAG pins in the PCI 9030;
therefore, the pull-up resistors must be externally added to the
PCI 9030.
11.2.2 Output Pins (Pin Type O)
This section discusses the pull-up and pull-down
resistor requirements for the following Local Bus
output pins—ADS#, ALE, BCLKo, BLAST#, CS[1:0]#,
EECS, EEDI, EESK, ENUM#, LA[23:2], LBE[3:0]#,
LEDon#, LGNT, LPMINT#, LRESETo#, LW/R#, RD#,
TDO, and WR#.
11-2
LPMESET
LINTi[2:1]
READY#
Signal
TRST#
MODE
LREQ
IEEE Standard 1149.1-1990 requires pull-up resistors
TMS
TCK
TDI
If configured as level-sensitive (default)
in INTCSR[9:8], connect to a pull-up or
pull-down resistor to hold the signal in an
inactive state, for the polarity configured
in INTCSR[4, 1] (default is active-low).
Unused pins can be tied to V
to hold the input in the inactive state
(V
configuration).
If used to trigger PME# assertion,
connect to a pull-down resistor to hold
the signal in the inactive state. If not
used, pull low or tie to V
Pull or drive low, or tie to V
Local Bus ownership to the PCI 9030.
Tie high for Multiplexed mode, or low for
Non-Multiplexed mode.
If enabled, connect to a pull-up resistor
to hold the signal in an inactive state.
If disabled or all local address spaces
(default) in LASxBRD and EROMBRD,
tie high or low.
If JTAG is not used, tie high or low.
If used, an external pull-up resistor
is required.
Must be pulled low during PCI RST#
assertion. If JTAG is not used, it is
recommended that TRST# always be
pulled low to place JTAG functionality in
the reset state and enable normal chip
logic operation. (Refer to PCI 9030
Errata #5.)
DD
for default active-low
Requirements
SS
.
SS
DD
to provide
or V
SS
11.2.2.1 Three-State Output Pins
Three-state (TS) output pins are ADS#, ALE, BLAST#,
CS[1:0]#,
TDO, and WR#.
The PCI 9030 drives Local Bus three-state output
signals when it owns the Local Bus, and floats Local
Bus three-state output signals when it does not own
the Local Bus (LGNT asserted). Three-state output
signals are also floated during PCI reset.
When the PCI 9030 is used in a system with multiple
masters on the Local Bus, pull-up and/or pull-down
resistors may be required on three-state output pins to
hold control signals in the inactive state when the
PCI 9030 does not own the Local Bus, and/or to
reduce noise coupling between Local Bus devices.
11.2.2.2 Totem-Pole Output Pins
Totem-pole (TP) output pins are BCLKo, EECS, EEDI,
EESK, LGNT, LPMINT#, and LRESETo#.
Totem-pole outputs are always driven, except when
the BD_SEL#/TEST input is high and the EEDO input
is low (IDDQ test state).
11.2.2.3 Open-Drain Output Pins
Open-drain (OD) output pins are ENUM# and
LEDon#.
requirements.)
Table 11-3. Output Pin Pull-Up and Pull-Down
Resistor Requirements
Pull-Up and Pull-Down Resistor Recommendations
LEDon#
ENUM#
Signal
© 2002 PLX Technology, Inc. All rights reserved.
(Refer
LA[23:2],
ENUM# is a three-state buffer that is
configured as an output; therefore, a
pull-up resistor is required to ensure the
buffer input value is in a known state.
LEDon# is an open-drain output that is
always enabled. HS_CSR[3] (default = 0)
controls whether LEDon# sinks current or
floats (default = OFF); therefore, neither a
pull-up nor pull-down resistor is required.
Note:
PCI RST# input is asserted.
to
LBE[3:0]#,
PCI 9030 Data Book Version 1.4
Table
LEDon# is also asserted while
Requirements
11-3
LW/R#,
for
resistor
RD#,