PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 192

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

µBGA
to
µBGA
MODE 11-2, 11-11, 13-3, 13-6
modes, bus
Multiplexed mode 11-2, 11-7, 11-9–11-11
N
NC (µBGA) 11-4, 13-6
networking 1-1
new capabilities
non-burst
Non-Multiplexed mode 11-9–11-11
NRAD, NRDD, NWAD, NWDD, and NXDA 2-8, 10-21–
O
operating ranges 12-1
output, general purpose
Index-6
serial EEPROM map 3-2
timing diagrams 3-10, 4-15
write 2-1, 10-4
product ordering and support A-1
layers, routing 13-7–13-8
package mechanical dimensions 13-4
PCB layout suggested land pattern 13-5
pinout 13-6
See Multiplexed mode and Non-Multiplexed mode
Bus mode 11-12–11-14
byte number and lane cross-reference 2-11
interface pin 11-1
Local Bus 1-3, 2-6
programmable Local Bus 1-3
recovery states 2-10
timing diagrams 4-9–4-31
functions support 10-5
linked list 7-1
Next_Cap Pointer 8-4
Pointer (CAP_PTR) 7-1, 10-1, 10-10
structure 3-7, 8-4, 9-1
support bit 7-1
VPD 9-1
See burst
Big/Little Endian byte number and lane
Bus mode 11-15–11-17
interface pin 11-1
Local Bus 1-3, 2-6
programmable Local Bus modes 1-3
recovery states 2-10
timing diagrams 4-9–4-26, 4-32–4-45
See Also internal wait states
See general purpose I/O
PCI r2.2
10-29
cycle 10-21, 10-23, 10-25, 10-27, 10-29
cross-reference 2-11
P
package mechanical dimensions
PAR 11-8, 13-3, 13-6
PCI 3-6, 3-7, 4-38
PCI 9030
PCI Bus 1-3, 2-1–2-2, 2-10, 11-11, 12-3, 12-4
PCI Bus Power Management Interface Specification,
PCI configuration registers 10-4–10-15
PCI industrial implementations 1-1
PCI Initiator, not supported 2-6
PCI Local Bus Specification, Revision 2.2
PCI Power Mgmt. r1.1 1-1, 7-1, 7-2, 7-3, 10-12
PCI r2.2
µBGA 13-4
PQFP 13-1
applications 1-2–1-3
clock 1-3, 1-4, 1-5, 3-1, 3-8, 4-2, 4-3, 4-13, 6-2, 10-12,
compared with PCI 9050 and 9052 1-5
compatibility with other PLX chips 1-4
product ordering and customer support A-1
SMARTarget features 1-3
access to internal registers 3-7
board healthy 8-2
CNTRL 10-35
cycles 2-1
disconnect 4-4
FIFO, response to full or empty 4-8
GPIOC 6-3
Hot Swap Ready Target device 1-1
input RST# 3-1
interface 2-1
Latency Timer, not supported 10-2, 10-6
Little Endian mode 2-1
local address spaces 4-4, 4-7
PCI Target operation 4-1, 4-4
PCISR 3-3, 7-1, 10-5
region 4-5, 4-6, 10-3, 10-8, 10-9
soft reset 7-1, 7-2
software reset 3-1
system bus interface pins 11-7–11-8
Target lock 4-1
transactions 4-4
V
VPD 9-1
wait states 2-1, 2-8
See PCI Power Mgmt. r1.1
address mapping 10-2
See PCI r2.2
1-1, 1-2, 1-5, 2-1, 3-6, 4-2, 4-42, 7-1, 9-1, 10-2, 10-16,
Revision 1.1
CC
10-34, 11-9, 12-3
10-17, 10-34, 11-1, 11-7
1-5
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4