PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 153

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

11
11.1
Tables in this section describe each PCI 9030 pin.
Table
information common to all Local Bus modes of
operation:
• Power and Ground
• Serial EEPROM Interface
• Test and Debug
• PCI System Bus Interface
• PCI Mode Independent Interface
• Local Bus Mode Independent Interface
Pins in Table 11-11 and Table 11-12 correspond to the
PCI 9030
Non-Multiplexed:
• Multiplexed Bus Mode Interface Pin Description
• Non-Multiplexed Bus Mode Interface Pin
For a visual of the chip pinout, refer to Section 13,
“Physical Specifications.”
The following table lists abbreviations used in this
section to represent various pin types.
Table 11-1. Pin Type Abbreviations
Note:
Note for PCI pins:
unless the PCI 9030 is being used in an embedded design.
Refer to PCI r2.2.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Abbreviation
(32-bit address/32-bit data)
Description (32-bit address/32-bit data)
DTS
STS
OD
I/O
TP
TS
O
I
A “#” in the pin name indicates active low.
11-5
PIN DESCRIPTION
PIN SUMMARY
Local
through
Driven three-state, driven high for one-half
CLK before float
Input only
Input and output
Output only
Open drain
Sustained three-state, driven high for one
CLK before float
Totem pole
Three-state
DO NOT pull up or down on any pins
Bus
Table
modes—Multiplexed
Pin Type
11-10
provide
and
pin
11.2
Except for a 50K pull-up resistor on EEDO and a
50K pull-down resistor on BD_SEL#/TEST, no internal
pull-up or pull-down resistors are present in the
PCI 9030. To prevent oscillation, unused inputs should
be terminated rather than left floating. The suggested
values for external pull-up and pull-down resistors are
1K to 10K Ohms.
11.2.1 Input Pins (Pin Type I)
This section discusses the pull-up and pull-down
resistor requirements for the following input pins—
BD_SEL#/TEST, BTERM#, CPCISW, EEDO, LCLK,
LINTi[2:1], LPMESET, LREQ, MODE, READY#, TCK,
TDI, TMS, TRST#. (Refer to Table 11-2 for resistor
requirements.)
Table 11-2. Input Pin Pull-Up and Pull-Down
Resistor Requirements
BD_SEL#/TEST
BTERM#
CPCISW
Signal
EEDO
LCLK
PULL-UP AND PULL-DOWN
RESISTOR RECOMMENDATIONS
For CompactPCI Hot Swap, pull up to
Early Power; otherwise, pull or tie low
because the internal 50K-Ohm pull-down
resistor is not sufficiently strong to
guarantee proper operation.
If enabled, connect to a pull-up resistor
to hold signal in an inactive state. If
disabled for all local address spaces
(default) in LASxBRD and EROMBRD,
tie high or low.
If CompactPCI Hot Swap is not used,
pull or tie low
Use an external pull-up resistor due
to the weak value (50K Ohms) of the
internal pull-up resistor. The pull-up
resistor must be pulled to Early Power
V
and normal V
A missing pull-up resistor for the EEDO
signal may intermittently bring the
PCI 9030 to a quiescent state. If no serial
EEPROM is present, can be tied to V
Local clock is required. Must start prior
to PCI RST# de-assertion.
DD
in CompactPCI Hot Swap platforms
Requirements
DD
in regular PCI platforms.
DD
11-1
.