PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 15

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Timing Diagrams
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
2-1 Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT). . . . . . . . . . . . . . . . . . . . 2-6
3-1 Initialization from Serial EEPROM (2K or 4K Bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-2 PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-3 PCI Configuration Read from PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-4 PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3-5 PCI Memory Read from Local Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
4-1 Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT). . . . . . . . . . . . . . . . . . . . 4-9
4-2 Local Level-Triggered Interrupt Asserting PCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4-3 Local Edge-Triggered Interrupt Asserting PCI Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4-4 GPIO[8:0] as Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4-5 Chip Select [3:0]# (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4-6 Initialization from Serial EEPROM (2K or 4K Bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4-7 PCI Configuration Write to PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4-8 PCI Configuration Read from PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4-9 PCI Memory Write to Local Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4-10 PCI Memory Read from Local Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4-11 PCI Target Burst Write with Delayed Write and Chip Select Enabled (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . 4-16
4-12 PCI Target Burst Write (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4-13 PCI Target Burst Write (16-Bit Local Bus), No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4-14 PCI Target Burst Write (16-Bit Local Bus), One Data-to-Data Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
4-15 PCI Target Burst Writes (8-Bit Local Bus), One Data-to-Data Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4-16 PCI Target Single Writes (16-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4-17 PCI Target Burst Write (8-Bit Local Bus), No Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
4-18 PCI Target Back-to-Back Single Writes (32-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
4-19 PCI Target Back-to-Back Burst Write Followed by Read (16-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
4-20 PCI Target Back-to-Back Burst Read Followed by Write (16-Bit Local Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
4-21 PCI Target Back-to-Back Burst Reads (16-Bit Local Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
4-22 PCI Target Single Write (32-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
4-23 PCI Target Single Read (32-Bit Local Bus), Multiplexed Mode Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
4-24 PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . 4-29
4-25 PCI Target Burst Read with Prefetch Enabled (32-Bit Local Bus),
4-26 PCI Target Non-Burst Write (8-Bit Local Bus), Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
4-27 PCI Target Single Write (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
4-28 PCI Target Single Read (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
4-29 PCI Target Single Read with One Wait State Using READY# Input (32-Bit Local Bus),
4-30 PCI Target Single Read with One Wait State Using Internal Wait State (32-Bit Local Bus),
4-31 PCI Target Non-Burst Write (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
4-32 PCI Target Non-Burst Read, Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
4-33 PCI Target Burst Write with Bterm Enabled (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . 4-38
4-34 PCI Target Burst Write with Bterm Disabled (32-Bit Local Bus), Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . 4-39
Prefetch Counter Set to 8, Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
Non-Multiplexed Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
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