PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 37

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Bus
Table 2-9. Byte Number and Lane Cross-Reference
2.2.5.1
Data is Lword aligned to the uppermost byte lane
(Address Invariance).
Table 2-10. Lword Lane Transfer—32-Bit Local Bus
Figure 2-5. Big/Little Endian—32-Bit Local Bus
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
First Transfer
Endian
Burst Order
31
31
Big
Byte Number
3
2
1
0
BYTE 3
BYTE 0
32-Bit Local Bus—
Big Endian Mode
Endian
Little
0
1
2
3
PCI Byte 0 appears on Local Data [31:24]
PCI Byte 1 appears on Local Data [23:16]
PCI Byte 2 appears on Local Data [15:8]
PCI Byte 3 appears on Local Data [7:0]
BYTE 1
BYTE 2
Little Endian
Big Endian
Multiplexed
LAD[23:16]
LAD[31:24]
LAD[15:8]
LAD[7:0]
Mode
BYTE 1
BYTE 2
Byte Lane
Byte Lane
Non-Multiplexed
LD[23:16]
LD[31:24]
LD[15:8]
BYTE 0
BYTE 3
LD[7:0]
Mode
0
0
2.2.5.2
For a 16-bit Local Bus, the PCI 9030 can be
programmed to use upper or lower word lanes.
Table 2-11. Upper Word Lane Transfer—
16-Bit Local Bus
Table 2-12. Lower Word Lane Transfer—
16-Bit Local Bus
Figure 2-6. Big/Little Endian—16-Bit Local Bus
First Transfer
Second Transfer
First Transfer
Second Transfer
31
15
Second Cycle
31
Burst Order
Burst Order
BYTE 3
BYTE 0
Big Endian
Big Endian Mode
16-Bit Local Bus—
BYTE 2
BYTE 1
Byte 0 appears on Local Data [31:24]
Byte 1 appears on Local Data [23:16]
Byte 2 appears on Local Data [31:24]
Byte 3 appears on Local Data [23:16]
Byte 0 appears on Local Data [15:8]
Byte 1 appears on Local Data [7:0]
Byte 2 appears on Local Data [15:8]
Byte 3 appears on Local Data [7:0]
Little Endian
16
0
15
15
First Cycle
BYTE 1
BYTE 0
Byte Lane
Byte Lane
Big Endian
PCI and Local Bus
BYTE 0
BYTE 1
Section 2
0
0
2-11
0