PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 35

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Bus
2.2.4.3
Note:
PCI 9030 internal register bit and BTERM# refers to the
PCI 9030 external signal.
2.2.4.3.1
As an input, BTERM# is asserted by external logic.
It instructs the PCI 9030 to break up a Burst cycle.
Table 2-6. Burst and Bterm on the Local Bus
On the Local Bus, BLAST# and BTERM# perform the
following:
• If Local Bus bursting is enabled for a Local Address
• If Bterm mode and BTERM# input are enabled
• BTERM# input is valid only when the PCI 9030
• BTERM# is used to indicate a Memory access
• If the internal wait state counter is programmed
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Single Cycle
Burst-4
Continuous
Burst
space (LASxBRD[0]=1 and/or EROMBRD[0]=1),
but Bterm mode (continuous burst) and BTERM#
input are disabled (LASxBRD[2]=0 and/or
EROMBRD[2]=0), the PCI 9030 bursts up to four
Data phases or to the next 16-byte boundary,
whichever occurs first. BLAST# is asserted at the
beginning of the last Data phase and a new ADS#
is asserted at the first Lword-aligned address
(LA[3:2]=00) for the next burst.
(LASxBRD[2]=1 and/or EROMBRD[2]=1) and
asserted, the PCI 9030 terminates the Burst cycle
at the end of the current Data phase without
generating BLAST#. The PCI 9030 generates
a new Burst transfer, starting with a new ADS#,
and terminating it normally using BLAST#.
is performing a PCI Target transaction.
is crossing a page boundary or requires a new
Address cycle.
to a non-zero value and Bterm mode and
the BTERM# input are enabled (LASxBRD[2]=1
and/or EROMBRD[2]=1), BTERM# input is not
sampled until the wait state counter reaches 0.
Mode
In the following sections, Bterm refers to the
Burst Mode and Continuous
Burst Mode (Bterm “Burst
Terminate” Mode)
Burst and Bterm Modes
Burst
0
0
1
1
Bterm
0
1
0
1
One ADS# per data (default)
One ADS# per data
One ADS# per four data
One ADS# per BTERM#
(refer to Section 2.2.4.3.3)
Result
• BTERM# always overrides READY#, even if
Note:
disabled (LASxBRD[2]=0 and/or EROMBRD[2]=0), the PCI 9030
performs the following:
In every case, it performs four data beats.
2.2.4.3.2
If Bterm mode (continuous burst) and BTERM# input
are disabled, and Local Bus bursting is enabled for a
Local Address space (LASxBRD[2, 0]=01 and/or
EROMBRD[2, 0]=01, respectively), bursting can start
on any Lword boundary and continue up to a 16-byte
address boundary. After data up to the boundary is
transferred, the PCI 9030 asserts a new Address cycle
(ADS#).
Table 2-7. Burst-4 Mode
2.2.4.3.3
If Bterm mode and BTERM# input are enabled, and
Local Bus bursting for a Local Address space is
enabled (LASxBRD[2, 0]=11 and/or EROMBRD[2, 0]
=11, respectively), the PCI 9030 can operate beyond
Burst-4 mode.
Bterm mode enables the PCI 9030 to perform long
bursts to devices that can accept bursts of longer than
four data. The PCI 9030 asserts one Address cycle
and continues to burst data. If a device requires a new
Address cycle (ADS#), it can assert BTERM# input to
cause the PCI 9030 to assert a new Address cycle.
The BTERM# input acknowledges the current Data
transfer (replacing READY#) and requests that a new
Address cycle be asserted (ADS#). The new address
is for the next Data transfer. If Bterm mode and
Bus Width
both signals are asserted. BTERM# executes
the ongoing transaction and causes the PCI 9030
to initiate a new Address/Data cycle for Burst
transactions.
•
•
•
32 bit
16 bit
8 bit
32-bit Local Bus—Bursts up to four Lwords
16-bit Local Bus—Bursts up to two Lwords
8-bit Local Bus—Bursts up to one Lword
If Bterm mode (continuous burst) and BTERM# input are
Burst-4 Mode
Four Lwords or up to a quad Lword boundary
(LA[3:2]=11)
Four words or up to a quad word boundary
(LA[2:1]=11)
Four bytes or up to a quad byte boundary
(LA[1:0]=11)
Continuous Burst Mode (Bterm
“Burst Terminate” Mode)
Burst
PCI and Local Bus
Section 2
2-9