PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 196

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

registers, hidden (PMDATASEL, PMDATASCALE)
to
registers, hidden (PMDATASEL, PMDATASCALE)
registers, new definitions summary 10-1
remap
reset
resistors 8-1, 11-1–11-3
retry delay timer 4-4
Revision ID 3-6, 10-5
RISC architecture 2-2
routing, board, µBGA 13-7–13-8
RST# 3-1, 11-8, 13-3, 13-6
S
serial EEPROM
Index-10
PCIMLR (not supported) 10-11
PCIREV 3-3, 10-5
PCISID 3-3, 10-10
PCISR 3-3, 7-1, 10-5
PCISVID 3-3, 10-4, 10-10
PMC 3-3, 3-5, 7-2, 10-12
PMCAPID 3-3, 7-1, 10-12
PMCSR 3-3, 3-5, 6-2, 7-2, 7-3, 10-1, 10-2, 10-13, 10-14,
PMCSR_BSE 10-13
PMDATA 3-5, 7-2, 7-3, 10-14, 10-37
PMDATASCALE 7-2, 7-3, 10-13, 10-37
PMDATASEL 7-2, 7-3, 10-14, 10-37
PMNEXT 3-3, 3-7, 7-1, 10-12
PROT_AREA 3-4, 9-2, 10-33
PVPD_NEXT 3-3, 3-7, 9-1, 10-15
PVPDAD 9-1, 10-15
PVPDATA 9-1, 10-15
PVPDCNTL 3-3, 9-1, 10-15
7-2–7-3, 10-37
local base address 4-7
PCI-to-Local addresses 4-5
serial EEPROM register load sequence 3-3
See Also map and mapping
initialization 4-5
platform 8-2
serial EEPROM 3-1–3-10
soft 7-1, 7-2
software 3-1, 10-35
accidental write to 9-2
CNTRL register 10-34–10-35
control 10-3
device ID and vendor ID registers 10-4
interface 1-4
interface pins 11-1, 11-5
internal registers access 2-6
PROT_AREA 10-33
random read and write 9-2
read control 1-5
read-only portion 9-1
system reconfiguration
10-37, 11-11
SERR# 11-8, 13-3, 13-6
setup and hold waveform, local input 12-3
signal names
signaling 1-4, 1-5
signals 2-3
silicon revision ID 1-4, 10-5
Single Cycle mode 2-9
SMARTarget Technology 1-1, 1-3
soft reset 7-1, 7-2
software
spaces 1-3, 2-10, 3-3, 4-1, 4-4, 4-7
spare pins (µBGA) 11-4, 13-6
specifications
states, basic bus 2-3
stepping 10-4
STOP# 11-8, 13-3, 13-6
strobe 11-14, 11-17
strobe timing, programmable read and write 1-1, 2-6,
subsystem ID and subsystem vendor ID 3-1, 10-10
system reconfiguration
reset and initialization 3-1–3-10
support 1-5
timing diagrams 4-13–4-15
vendor ID and device ID registers 10-4
VPD 9-1–9-2
write 9-2, 10-5, 10-10, 10-11, 10-14, 10-15, 10-18
Write-Protected Address Boundary register
Local Bus mode independent interface 11-9
Multiplexed Bus mode interface 11-12
Non-Multiplexed Bus mode interface 11-15
PCI system bus interface 11-7–11-8
power and ground 11-4
serial EEPROM interface 11-5
test and debug 11-6
synchronous 12-3, 12-4
See Also PCI Target
connection control 8-2
development 1-1
Hot Swap system 8-3
PCI 4-5
reset 3-1, 10-35
local address space bus region descriptor
local address space local base address registers 10-19–
local address space range registers 10-16–10-17
PCI base address registers 10-8–10-9
register address mapping 10-2, 10-3
See electrical specifications, or general electrical
See configuration
10-22–10-30
(PROT_AREA) 10-1, 10-3, 10-33
registers 10-21–10-27
10-20
specifications
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4