PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 45

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

New Capabilities Function Support
PCI Base Address for Accesses to Local Address
Spaces 0, 1, 2, and 3. The system BIOS uses these
registers to assign a PCI address space segment for
accesses to Local Address Space 0, 1, 2, and 3. The
PCI address range occupied by this space is
determined by the Local Address Space Range
registers.
FFFFFFFF to these registers, then reads back a value
determined by the range. The Host then writes the
base address to the upper bits of these registers.
PCI Expansion ROM Base Address. The system
BIOS uses this register to assign a PCI address space
segment for accesses to the Expansion ROM. The
PCI address range occupied by this space is
determined by the Expansion ROM Range register.
During initialization, the Host writes FFFFFFFF to this
register, then reads back a value determined by the
range. The Host then writes the base address to the
upper bits of this register.
PCI Interrupt Line. Indicates to which system
interrupt controller(s) input the interrupt line is
connected. The PCI 9030 does not use this value,
rather the value is used by device drivers and
operating systems for priority and vector information.
Values in this register are system-architecture specific.
PCI Interrupt Pin. This register specifies the interrupt
request pin (if any) to be used. The PCI 9030 supports
INTA#, but not INTB#, INTC#, nor INTD#.
3.4.2
The PCI 9030 PCI Configuration registers can be
accessed from the PCI Bus with a Type 0
Configuration cycle.
All other PCI 9030 internal registers can be accessed
by a Memory cycle, with the PCI Bus address that
matches the base address specified in PCI Base
Address 0 (PCIBAR0[31:4]) for the PCI 9030 Memory-
Mapped Configuration register. These registers can
also be accessed by an I/O cycle, with the PCI Bus
address matching the base address specified in
PCI Base Address 1 (PCIBAR1[31:2] for the PCI 9030
I/O-Mapped Configuration register.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
PCI Bus Access to
Internal Registers
During
initialization,
the
host
writes
All PCI Read or Write accesses to the PCI 9030
registers can be Byte, Word, or Lword accesses. All
PCI Memory accesses to the PCI 9030 registers can
be Burst or Non-Burst accesses. The PCI 9030
responds with a PCI Bus disconnect for all Burst I/O
accesses (PCIBAR1[31:2]) to the PCI 9030 Internal
registers.
3.5
The New Capabilities Function Support includes PCI
Power Management, Hot Swap, and VPD features, as
listed in the following table. [For further information on
these features, refer to Section 7, “PCI Power
Management,” Section 8, “CompactPCI Hot Swap,”
and Section 9, “PCI Vital Product Data (VPD).”]
Table 3-3. New Capabilities Function Support Features
First
(Power Management)
Second
Hot Swap)
Third
(VPD)
New Capability
Function
NEW CAPABILITIES
FUNCTION SUPPORT
Serial EEPROM Reset and Initialization
40h, which is pointed to,
from CAP_PTR [7:0].
48h, which is pointed to,
from PMNEXT[7:0].
4Ch, which is pointed to,
from HS_NEXT[7:0].
Because PVPD_NEXT[7:0]
defaults to zero (0), this indicates
that VPD is the last PCI 9030
New Capability Function
Support feature.
Offset Location
PCI Register
Section 3
3-7