PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 188

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

bus modes
to
bus modes
bus region descriptor registers 2-4, 3-4, 4-5, 4-6,
bus states 2-3
byte conversion, Big/Little Endian 1-1, 1-3
byte enables 2-1, 2-10, 4-2
byte merging 2-1–2-2
C
C/BE[3:0]# 2-1, 4-2, 11-7, 13-3, 13-6
cache line size, PCI 3-6, 10-6
CAP_PTR 3-3, 3-7, 7-1, 10-10
capacitance 12-1
chip select 11-9
clocks 1-4, 4-2, 7-1, 10-34, 11-8
CNTRL 1-5, 2-5, 3-1, 3-4, 4-1, 4-2, 4-4, 4-8, 10-34–
command codes, PCI Target 2-1
CompactPCI Hot Swap 1-2, 8-1–8-4
configuration
Index-2
See Multiplexed mode and Non-Multiplexed mode
address mapping 10-3
PCI Target 4-7
See Also C/BE[3:0]# and LBE[3:0]#
base address registers 5-1–5-4, 10-31
CNTRL 10-35
IDSEL and initialization device 11-7
local 5-1–5-4, 10-3
LSW and MSW 3-4
pins 11-9
programmable 1-2, 1-3
registers, address mapping 10-3
serial EEPROM 10-35, 11-5
SMARTarget 1-1
timing diagrams 4-12, 4-16, 5-3–5-4
bus access 11-12, 11-15
delay 10-35
EESK 3-1, 11-5
Local 6-2, 11-1, 11-10, 12-3–12-5
PCI 1-3, 1-5, 3-1, 3-8, 4-3, 4-4, 4-13, 6-2, 10-12, 11-9,
serial EEPROM 3-1, 10-35, 11-5
compliant 1-3
registers 10-1, 10-2, 10-14
accesses 1-4, 3-1, 7-2, 10-13
Big/Little Endian 4-4
BTERM# 11-12, 11-15
bus-width 11-13, 11-16
command type 2-1
control/status register 8-3
CS[1:0]# 11-9
cycles 3-7, 7-1, 7-3
Hot Swap 8-1, 8-3
deadlock, avoided with PMW
10-8, 10-9, 10-21–10-29, 11-14, 11-17
10-35
11-10, 12-3
Continuous Burst mode 2-9–2-10
Continuous Prefetch mode 4-3, 4-4
control registers 10-33–10-37
control signals 2-3
Control/Status 2-4–2-5
controller, programmable interrupt 1-1, 1-3
conversion, Big/Little Endian 1-1, 1-3, 1-5, 4-4
counter
CPCISW 8-1, 11-1, 11-9, 13-3, 13-6
CPU
CS[1:0]# 11-9, 13-3, 13-6
CS0BASE 3-4, 10-31
CS1BASE 3-4, 10-31
CS2# 11-3, 11-9, 13-3, 13-6
CS2BASE 3-4, 10-32
CS3# 11-3, 11-9, 13-3, 13-6
CS3BASE 3-4, 10-32
D
D
data/wait bus state 2-3
deadlock, avoided with PMW
3hot
I/O-mapped register 3-7
IDSEL 11-7
load information 1-4
local registers 3-1, 3-6
memory-mapped register 3-7
new capabilities 9-1
new capability linked list 10-1
PCI cycles 7-1
PCI registers 3-6, 3-7, 10-4–10-15
power management 7-2
read and write 11-7
register space 1-4
registers 3-1, 4-1, 11-9, 11-12, 11-15
serial EEPROM 3-1
software reset 3-1
space 8-3, 9-1, 10-1
subsystem ID and subsystem vendor ID 1-4
system reconfiguration 8-1, 8-3
Target bus-width 11-16
timing diagrams, initialization 3-9–3-10, 4-14–4-15
VPD 9-1
wait states counter 2-8
address mapping 10-3
prefetch 1-5, 4-1
wait states 2-8
host 2-6, 8-3
local 7-3, 10-13
1-3
register bits 10-21, 10-23, 10-25, 10-27, 10-29
timing diagrams, settings in 4-30, 4-40
10-12
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4