PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 189

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

debug
decode 4-5
Delayed Read mode, PCI Target 1-5, 4-2, 4-3
Delayed Write mode, PCI Target 1-3, 1-5, 4-3, 10-34
descriptors, bus region 2-4, 3-4, 4-5, 10-8, 10-9,
device
DEVSEL# 11-7, 13-3, 13-6
Direct Slave
disconnect
DSP devices 2-2
E
Early Power 8-1, 8-2, 11-1, 11-6
EECS 11-5, 13-3, 13-6
EEDI 11-5, 13-3, 13-6
EEDO 11-1, 11-5, 11-6, 13-3, 13-6
EESK 11-5, 13-3, 13-6
electrical specifications 12-1–12-5
embedded
Endian, Big/Little 2-10–2-12
ENUM# 1-2, 8-1, 8-3, 10-14, 11-2, 11-7, 13-3, 13-6
EROMBA 3-4, 4-4, 10-20
EROMBRD 3-4, 4-5, 10-29
EROMRR 3-3, 4-4, 10-10, 10-18
expansion ROM 1-3, 2-10, 3-3, 4-1, 4-4, 4-7, 10-2, 10-3
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
interface and port 11-18
pins 11-6
address enable 10-10
CNTRL 10-34
read accesses 2-10
timing diagram 4-16, 5-4
address mapping 10-3
chip select 5-1, 5-2
configuration header 3-6
ID 3-1, 3-3, 9-1, 10-4
See PCI Target
after transfer for all PCI Target I/O accesses 4-1
Flush Read FIFO 10-35
PCI Bus 3-7, 4-4
PCI r2.2 Features Enable 4-42
PCI Write 10-35
design 11-1
systems 1-1
Byte Lane mode and byte ordering 10-22, 10-24, 10-26,
conversion 1-1, 1-3, 1-5, 4-4
Local Bus 2-10–2-11
PCI Bus Little Endian mode 2-1
Local Bus width 10-29
space 3-7, 4-1, 4-7
10-21–10-29, 11-14, 11-17
access, address decode enable 10-10
input enables, BTERM# and READY# 10-29
10-28, 10-30
external wait states 2-10, 4-1, 4-41
F
FIFOs 10-35
flush 4-2
FRAME# 11-7, 13-3, 13-6
G
general purpose I/O 6-1–6-3, 11-3, 11-9, 13-3, 13-6
generator
GPIO
GPIO[7:4] 4-11, 6-5, 11-3, 11-13, 11-15, 13-3, 13-6
GPIO[8, 3:0] 4-11, 6-5, 11-3, 11-10, 13-3
GPIOC 6-3, 10-36–10-37
H
header
hidden registers 3-4, 3-5, 7-2, 7-3, 10-1, 10-3, 10-13,
High-Polarity mode 10-33
hold waveform 12-3
Hot Swap 8-1–8-4, 10-14
Hot-Plug system driver 8-3
HS_CNTL 3-3, 8-4, 10-14
HS_CSR 1-2, 8-1, 8-3, 10-14, 11-2
HS_NEXT 3-3, 3-7, 8-4, 10-14
I
I/O
CNTRL, in 10-35
Continuous Burst mode 2-10
PCI Target 1-3–1-5, 3-1, 4-1–4-3, 4-4
response to full/empty 4-8
control register (GPIOC) 10-36–10-37
timing diagrams 4-11, 6-5
See Also GPIO-related entries
programmable interrupt 1-1, 1-3
programmable wait states 4-1, 11-9, 11-12, 11-15
programmable general purpose I/O 1-3
SMARTarget 1-1
See Also general purpose I/O
format 10-18
PCI type 3-6
Control/Status register (HS_CSR) 1-2, 8-1
Silicon 1-2
See Also CompactPCI
accelerator 1-1
accesses 2-1, 4-4, 10-7, 10-13
base address 10-7
buffers 1-2, 8-1, 8-2, 11-4
10-14, 10-37
Local Address 4-1
remap 10-20
disabled in D
internal registers 3-7
3hot
state 7-2
debug
Index-3
to I/O