PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 155

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Pull-Up and Pull-Down Resistor Recommendations
11.2.3 I/O Pins (Pin Type I/O)
This section discusses the pull-up and pull-down
resistor requirements for the following Local Bus I/O
pins—GPIO0/WAITo#,
CS2#,
GPIO6/LA25, GPIO7/LA24, GPIO8, LAD/LD[31:0].
The PCI 9030 drives Local Bus I/O signals when it
owns the Local Bus, and floats Local Bus I/O signals
when it does not own the Local Bus (LGNT asserted).
During PCI reset, the PCI 9030 drives the GPIO4/
LA27, GPIO5/LA26, GPIO6/LA25, GPIO7/LA24, and
LAD/LD[31:0] signals low. (Refer to Table 11-4 for
resistor requirements and PCI 9030 Errata #4.)
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
GPIO3/CS3#,
GPIO4/LA27,
GPIO1/LLOCKo#,
GPIO5/LA26,
GPIO2/
Table 11-4. I/O Pin Pull-Up and Pull-Down
Resistor Requirements
GPIO1/LLOCKo#
GPIO0/WAITo#
LAD/LD[31:0]
GPIO2/CS2#
GPIO3/CS3#
GPIO4/LA27
GPIO5/LA26
GPIO6/LA25
GPIO7/LA24
Signal
GPIO8
If GPIO[8:0] are configured as inputs and
not used, pull or tie these pins to V
V
the following pins are configured as
inputs—GPIO0/WAITo#, GPIO1/
LLOCKo#, GPIO2/CS2#, GPIO3/CS3#,
and GPIO8.
Note:
regarding the GPIO[8:0] pins which,
when configured as outputs, are floated
when the PCI 9030 does not own the
Local Bus.
Connect unused Data Bus pins to a
pull-up or pull-down resistor. Depending
upon design, it is recommended to add
resistors to all Data pins. When reading
from a local device, the LAD/LD lines are
effectively floated, and if the local device
is not driving these pins (such as during
wait states), then noise can couple into
the LAD/LD inputs.
SS
. Under default register configuration,
Refer to PCI 9030 Errata #2,
Requirements
Pin Description
Section 11
DD
11-3
or