PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 158

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
Table 11-8. Test and Debug Pins
11-6
BD_SEL#
TEST
TCK
TDI
TDO
TMS
TRST#
Total
Symbol
Board Select
Test Pin
Test Clock
Input
Test Data In
Test Data
Output
Test Mode
Select
Test Reset
Signal Name
Total
Pins
1
1
1
1
1
1
6
Type
PCI
Pin
TS
O
I
I
I
I
I
Bias Voltage
CompactPCI
No Connect
Precharge
Hot Swap
1V
1V
1V
1V
1V
Number
PQFP
112
165
168
167
166
164
Pin
© 2002 PLX Technology, Inc. All rights reserved.
Number
µBGA
G11
Pin
A6
A5
C5
B5
E6
Pinout Common to All Bus Modes
CompactPCI Hot Swap Systems:
Should be pulled high externally. The
pull-up resistor needs to be connected
to Early Power.
Non-Hot Swap and other Systems:
Should be pulled low externally.
In combination with EEDO:
Used as an IDDQ test enable pin. When
pulled high, all outputs except LEDon#
are placed in three-state, and PCI Hot
Swap precharge resistors are active.
When pulled low, all outputs remain in
normal operation and PCI Hot Swap
precharge resistors are not active.
Clock source for the PCI 9030 test
access port (TAP). The maximum clock
rate into the TCK pin is LCLK rate or
less than one-half of the LCLK rate.
Used to input serial data into the TAP.
When the TAP enables this pin, it is
sampled on the rising edge of TCK and
the data is input to the selected TAP
Shift register.
Note:
Used to transmit data from the PCI 9030
TAP. Data from the selected TAP Shift
registers is shifted out on TDO.
Sampled by TAP on the rising edge of
TCK. The TAP state machine uses the
TMS pin to determine the mode in which
the TAP operates.
Note: Not used to select JTAG
operation.
Reset used by JTAG testers. TRST#
must be asserted during PCI RST#
assertion; otherwise, the PCI 9030 can
initialize into an undefined state,
precluding normal logic operation.
If JTAG is not used, it is recommended
that TRST# always be pulled low to put
JTAG functionality into the reset state
and enable normal chip logic operation.
PCI 9030 Data Book Version 1.4
No internal pull-up.
Function