PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 195

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

product ordering and support
programmable
Programming Interface 0 1-2, 8-1, 8-4, 10-14
PROT_AREA 3-4, 9-2, 10-33
pull-up/pull-down resistors 8-1, 11-1–11-3
PVPD_NEXT 3-3, 3-7, 9-1, 10-15
PVPDAD 9-1, 10-15
PVPDATA 9-1, 10-15
PVPDCNTL 3-3, 9-1, 10-15
R
ranges, operating 12-1, 12-2
RD# 2-4, 10-22–10-30, 11-14, 11-17, 13-3, 13-6
read 2-1
Read Ahead mode, PCI Target 1-1, 3-1, 4-3, 10-35
read strobe delay 1-1, 2-6, 10-22–10-30, 11-14, 11-17
READY# 2-5, 2-8, 11-2, 11-14, 11-17, 13-3, 13-6
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Local Bus 4-3
memory mapping 2-1–2-2
PCI Target 4-1–4-4, 10-21–10-29
A-1
bursts 1-1, 1-3
chip select 1-2, 5-1–5-2
FIFOs, zero wait state burst 1-3
internal registers 3-1, 4-1
Prefetch Counter 1-5
wait state generator 11-12, 11-14, 11-15
wait states 1-3, 1-5
accesses 2-10, 3-7, 4-4
FIFOs 1-3, 1-5, 2-10, 4-4
Local Bus accesses 2-10
PCI Configuration timing diagram 3-9, 4-14
PCI initialization 4-5
PCI Memory timing diagrams 3-10, 4-15
PCI Power mode example 7-3
PCI r2.2 Features Enable 4-42
PCI Target 1-3, 1-5, 3-1, 4-1, 4-2, 4-3, 4-4, 4-8, 10-35
programmable strobe timing on local bus 1-1
random read and write 9-2
registers 10-4–10-37
sequential read only 9-1
serial EEPROM 1-5, 3-1–3-2, 9-2
timing diagrams See timing diagrams 4-33
VPD 9-1–9-2
write PCI power management 7-1
Prefetch mode, in addition to 4-1
read accesses 2-10
supported by PCI 9030 1-3
timing diagram 4-43
expansion ROM bus region descriptor register 10-29
input 2-10, 10-21, 10-23, 10-25, 10-27
reconfiguration, system
recovery states 2-3, 2-10
register addresses 1-5, 10-2–10-3
registers
timeout logic, SMARTarget 1-1
timing diagram 4-34
wait states 4-1
See configuration
CAP_PTR 3-3, 3-7, 7-1, 10-10
CNTRL 1-5, 2-5, 3-1, 3-4, 4-1, 4-2, 4-4, 4-8, 10-34–10-35
CS0BASE 3-4, 10-31
CS1BASE 3-4, 10-31
CS2BASE 3-4, 10-32
CS3BASE 3-4, 10-32
EROMBA 3-4, 4-4, 10-20
EROMBRD 3-4, 4-5, 10-29
EROMRR 3-3, 4-4, 10-10, 10-18
GPIOC 6-3, 10-36–10-37
HS_CNTL 3-3, 8-4, 10-14
HS_CSR 1-2, 8-1, 8-3, 10-14
HS_NEXT 3-3, 3-7, 8-4, 10-14
INTCSR 3-4, 6-2, 10-33
LAS0BA 3-3, 4-4, 4-7, 10-8, 10-19
LAS0BRD 2-8, 3-4, 4-3, 4-5, 10-21
LAS0RR 3-3, 4-4, 10-8, 10-16
LAS1BA 3-4, 4-4, 4-7, 10-8, 10-19
LAS1BRD 2-8, 3-4, 4-3, 4-5, 10-23
LAS1RR 3-3, 4-4, 10-8, 10-16
LAS2BA 3-4, 4-4, 10-9, 10-20
LAS2BRD 2-8, 3-4, 4-3, 4-5, 10-25
LAS2RR 3-3, 4-4, 10-9, 10-17
LAS3BA 3-4, 4-4, 10-9, 10-20
LAS3BRD 2-8, 3-4, 4-3, 4-5, 10-27
LAS3RR 3-3, 4-4, 10-9, 10-17
PCIBAR0 3-7, 4-4, 10-7
PCIBAR1 3-7, 4-4, 10-7
PCIBAR2 4-4, 10-8
PCIBAR3 4-4, 10-8
PCIBAR4 4-4, 10-9
PCIBAR5 4-4, 10-9
PCIBISTR (not supported) 10-6
PCICCR 3-3, 10-5
PCICIS (not supported) 10-10
PCICLSR 3-6, 10-6
PCICR 6-2, 10-4
PCIERBAR 3-7, 4-4, 10-10
PCIHTR 3-6, 10-6
PCIIDR 3-3, 10-4
PCIILR 3-3, 10-11
PCIIPR 3-3, 10-11
PCILTR (not supported) 10-6
PCIMGR (not supported) 10-11
product ordering and support
to registers
Index-9