LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet - Page 100

• Manufacturer Part Number: LPC1857_53
• Description: The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 15.
T
[1]
LPC1857_53
Objective data sheet
Symbol
T
T
SSP master
t
t
t
t
SSP slave
t
t
t
t
DS
DH
v(Q)
h(Q)
DS
DH
v(Q)
h(Q)
amb
cy(PCLK)
cy(clk)
T
main clock frequency f
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
= 25
cy(clk)

= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
C; V
Parameter
PCLK cycle time
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time
data set-up time
data hold time
data output valid time
data output hold time
Dynamic characteristics: SSP pins in SPI mode
DD(REG)(3V3)
11.7 SSP interface
main
= 3.3 V. Simulated values.
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
Conditions
full-duplex mode
when only
transmitting
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
in SPI mode
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 December 2011
main
. The clock cycle time derived from the SPI bit rate T
[1]
Min
<tbd>
-
-
-
-
-
-
<tbd>
<tbd>  T
<tbd>
-
-
cy(PCLK)
32-bit ARM Cortex-M3 microcontroller
+
Typ
40
20
7.2
5.4
3.8
1.7
-
-
-
-
LPC1857/53
Max
-
-
-
-
-
-
-
-
-
+ <tbd>
<tbd>  T
+ <tbd>
<tbd>  T
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
cy(PCLK)
cy(PCLK)
100 of 131
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns